User manual ZILOG Z80 FAMILY

[. . . ] Z80 Family CPU User Manual User Manual UM008003-1202 ZiLOG Worldwide Headquarters · 532 Race Street · San Jose, CA 95126-3432 Telephone: 408. 558. 8500 · Fax: 408. 558. 8300 · www. ZiLOG. com Z80 CPU User's Manual This publication is subject to replacement by a later edition. To determine whether a later edition exists, or to request copies of publications, contact: ZiLOG Worldwide Headquarters 910 E. Hamilton Avenue Campbell, CA 95008 Telephone: 408. 558. 8500 Fax: 408. 558. 8300 www. ZiLOG. com Document Disclaimer ZiLOG is a registered trademark of ZiLOG Inc. All other products and/or service names mentioned herein may be trademarks of the companies with which they are associated. [. . . ] For SUB instructions, N is set to 1. Add/Subtract Flag The Decimal Adjust Accumulator instruction (DAA) uses this flag to distinguish between ADD and SUBTRACT instructions. For all SUBTRACT instructions, N sets to 1. Parity/Overflow Flag (P/V) This flag is set to a specific state depending on the operation performed. For arithmetic operations, this flag indicates an Overflow condition when the result in the Accumulator is greater than the maximum possible number UM008003-1202 Z80 Instruction Set Z80 CPU User's Manual 78 (+127) or is less than the minimum possible number (­128). This Overflow condition is determined by examining the sign bits of the operands. When adding operands with like signs and the result has a different sign, the Overflow Flag is set, for example: +120 +105 +225 = = = 0111 0110 1110 1000 1001 0001 ADDEND AUGEND (-95) SUM The two numbers added together resulted in a number that exceeds +127 and the two positive operands have resulted in a negative number (-95), which is incorrect. For example: +127 (-) -64 +191 0111 1100 1011 1111 0000 1111 MINUEND SUBTRAHEND DIFFERENCE The minuend sign has changed from a Positive to a negative, giving an incorrect difference. Another method for identifying an Overflow is to observe the Carry to and out of the sign bit. If there is a Carry in and no Carry out, or if there is no Carry in and a Carry out, then Overflow has occurred. This flag is also used with logical operations and rotate instructions to indicate the resulting parity is Even. During search instructions (CPI, CPIR, CPD, CPDR) and block transfer instructions (LDI, LDIR, LDD, LDDR), the P/V Flag monitors the state of the UM008003-1202 Z80 Instruction Set Z80 CPU User's Manual 79 Byte Count Register (BC). When decrementing, if the byte counter decrements to 0, the flag is cleared to 0, otherwise the flag is set to1. During LD A, I and LD A, R instructions, the P/V Flag is set with the value of the interrupt enable flip-flop (IFF2) for storage or testing. When inputting a byte from an I/O device with an IN r, (C), instruction, the P/V Flag is adjusted to indicate the data parity. Half Carry Flag The Half-Carry Flag (H) is set (1) or cleared (0) depending on the Carry and Borrow status between Bits 3 and 4 of an 8-bit arithmetic operation. This flag is used by the Decimal Adjust Accumulator instruction (DAA) to correct the result of a packed BCD add or subtract operation. The H Flag is set (1) or cleared (0) according to the following table: H Flag Add 1 0 Subtract A Carry occurs from Bit 3 to Bit 4 A Borrow from Bit 4 occurs No Carry occurs from Bit 3 to Bit 4 No Borrow from Bit 4 occurs Zero Flag The Zero Flag (Z) is set (1) or cleared (0) if the result generated by the execution of certain instructions is 0. For 8-bit arithmetic and logical operations, the Z flag is set to a 1 if the resulting byte in the Accumulator is 0. For compare (Search) instructions, the Z flag is set to 1 if the value in the Accumulator is equal to the value in the memory location indicated by the value of the Register pair HL. When testing a bit in a register or memory location, the Z flag contains the complemented state of the indicated bit (see "Bit b, s"). UM008003-1202 Z80 Instruction Set Z80 CPU User's Manual 80 When inputting or outputting a byte between a memory location and an I/O device (INI, IND, OUTI, and OUTD), if the result of decrementing the B Register is 0, the Z flag is 1, otherwise the Z flag is 0. Also for byte inputs from I/O devices using IN r, (C), the Z flag is set to indicate a 0-byte input. Sign Flag The Sign Flag (S) stores the state of the most-significant bit of the Accumulator (bit 7). When the Z80 performs arithmetic operations on signed numbers, the binary twos-complement notation is used to represent and process numeric information. The binary equivalent of the magnitude of a positive number is stored in bits 0 to 6 for a total range of from 0 to 127. A negative number is represented by the twos complement of the equivalent positive number. [. . . ] Register B may be used as a byte counter, and its decremented value is placed on the top half (A8 through A15) of the address bus. The byte to be output is placed on the data bus and written to a selected peripheral device. M Cycles 4 Condition Bits Affected: S is unknown Z is set if B­1 = 0; reset otherwise H is unknown P/V is unknown N is set C is not affected Example: If the contents of register C are 07H, the contents of register B are 10H, the contents of the HL register pair are 100014, and the contents of memory address 1000H are 5914, then after thee execution of OUTI register B contains 0FH, the HL register pair contains 1001H, and byte 59H is written to the peripheral device mapped to I/O port address 07H. 4. 00 UM008003-1202 Z80 Instruction Set Z80 CPU User's Manual 283 OTIR Operation: Op Code: (C) ¬ (HL), B ¬ B -1, HL ¬ HL + 1 OTIR 1 1 1 0 1 1 0 1 1 0 1 0 0 1 1 1 ED B3 Description: The contents of the HL register pair are placed on the address bus to select a location in memory. [. . . ]