User manual ZILOG Z80-CPU

[. . . ] Z80 Family CPU User Manual User Manual 80 =L/2* :RUOGZLGH +HDGTXDUWHUV ( +DPLOWRQ $YHQXH &DPSEHOO &$ 7HOHSKRQH )D[ ZZZ=L/2*FRP = &38 8VHUV 0DQXDO This publication is subject to replacement by a later edition. To determine whether a later edition exists, or to request copies of publications, contact: ZiLOG Worldwide Headquarters 910 E. Hamilton Avenue Campbell, CA 95008 Telephone: 408. 558. 8500 Fax: 408. 558. 8300 www. ZiLOG. com Document Disclaimer ZiLOG is a registered trademark of ZiLOG Inc. All other products and/or service names mentioned herein may be trademarks of the companies with which they are associated. [. . . ] These general-purpose registers are used for a wide range of applications. They also simplify programing, specifically in ROM-based systems where little external read/write memory is available. $ULWKPHWLF /RJLF 8QLW $/8 The 8-bit arithmetic and logical instructions of the CPU are executed in the ALU. Internally, the ALU communicates with the registers and the external data bus by using the internal data bus. Functions performed by the ALU include: 80 2YHUYLHZ < %27 7UGT U /CPWCN Add Subtract Logical AND Logical OR Logical Exclusive OR Compare Left or Right Shifts or Rotates (Arithmetic and Logical) Increment Decrement Set Bit Reset Bit Test bit , QVWUXFWLRQ 5HJLVWHU DQG &38 &RQWURO As each instruction is fetched from memory, it is placed in the INSTRUCTION register and decoded. The control sections performs this function and then generates and supplies the control signals necessary to read or write data from or to the registers, control the ALU, and provide required external control signals. 3, 1 '(6&5, 37, 21 2YHUYLHZ The Z80 CPU I/O pins are illustrated in Figure 3 and the function of each is described in the following paragraphs. 80 2YHUYLHZ < %27 7UGT U /CPWCN M1 MREQ IORQ RD WR RFSH HALT WAIT CPU Control INT NMI RESET CPU Bus Control BUSRQ BUSACK 27 19 20 21 22 28 18 24 16 17 26 25 23 System Control Z80 CPU 30 31 32 33 34 35 36 37 38 39 40 1 2 3 4 5 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 Address Bus CLK +5V GND 6 11 29 14 15 12 8 7 9 10 13 D0 D1 D2 D3 D4 D5 D6 D7 Data Bus )LJXUH = , 2 3LQ &RQILJXUDWLRQ 3LQ )XQFWLRQV $$ Address Bus (output, active High, tristate). The Address Bus provides the address for memory data bus exchanges (up to 64 Kbytes) and for I/O device exchanges. 80 2YHUYLHZ < %27 7UGT U /CPWCN %86$&. Bus Acknowledge (output, active Low). Bus Acknowledge indicates to the requesting device that the CPU address bus, data bus, and control signals MREQ, IORQ RD, and WR have entered their high-impedance states. The external circuitry can now control these lines. %865(4 Bus Request (input, active Low). Bus Request has a higher priority than NMI and is always recognized at the end of the current machine cycle. BUSREQ forces the CPU address bus, data bus, and control signals MREQ IORQ, RD, and WR to go to a high-impedance state so that other devices can control these lines. BUSREQ is normally wired-OR and requires an external pull-up for these applications. Extended BUSREQ periods due to extensive DMA operations can prevent the CPU from properly refreshing dynamic RAMS. '' Data Bus (input/output, active High, tristate). D7D0 constitute an 8-bit bidirectional data bus, used for data exchanges with memory and I/O. +$/7 HALT State (output, active Low). HALT indicates that the CPU has executed a HALT instruction and is waiting for either a non-maskable or a maskable interrupt (with the mask enabled) before operation can resume. During HALT, the CPU executes NOPs to maintain memory refresh. , 17 Interrupt Request (input, active Low). The CPU honors a request at the end of the current instruction if the internal software-controlled interrupt enable flip-flop (IFF) is enabled. INT is normally wired-OR and requires an external pull-up for these applications. 80 2YHUYLHZ < %27 7UGT U /CPWCN , 254 Input/Output Request (output, active Low, tristate). IORQ indicates that the lower half of the address bus holds a valid I/O address for an I/O read or write operation. IORQ is also generated concurrently with M1 during an interrupt acknowledge cycle to indicate that an interrupt response vector can be placed on the data bus. 0 Machine Cycle One (output, active Low). M1, together with MREQ, indicates that the current machine cycle is the opcode fetch cycle of an instruction execution. M1 together with IORQ, indicates an interrupt acknowledge cycle. 05(4 Memory Request (output, active Low, tristate). MREQ indicates that the address bus holds a valid address for a memory read of memory write operation. 10, Non-Maskable Interrupt (input, negative edge-triggered). [. . . ] q A9 &" q A9 &# q A9 &$ q A9 "% q EXT, ADDR IMPLIED (nn) "! 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(nn) REG. PUSH Instructions IND. (SP) NOTE: The Push & Pop instruction adjust the SP after every execution. POP Instructions 80 = &38 , QVWUXFWLRQ 'HVFULSWLRQ < %27 7UGT U /CPWCN 7DEOH ([FKDQJHV (; DQG (;; , PSOLHG $GGUHVVLQJ $) IMPLIED AF BC DE HL DE REG. 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