User manual ZILOG Z8 ENCORE NVDS OPERATION IN THE Z8 ENCORE AND Z8 ENCORE XP APPLICATION NOTE

[. . . ] These routines save the working register set before they are used (hence, 16 bytes of stack space is needed). After finishing the call to these routines, the working register set of the user code is recovered. AN031001-0710 Page 2 of 9 NVDS Operation in the Z8 Encore!® and Z8 Encore!XP® MCU's Application Note This section discusses the following topics in detail: · · · · · · Interrupt Handling During NVDS Operation Flash Frequency Register Initialization NVDS Write Operation NVDS Read Operation Power Failure Protection Optimizing NVDS Memory Usage for Execution Speed When the Z8 Encore!XP F042A Series device is in the DEBUG Mode, you can view the NVDS memory locations by performing the following steps in ZDS II: 1. [. . . ] NVDS byte writes to invalid addresses (those exceeding the NVDS array size) have no effect. Illegal write operations have a 2 µs (F082A series) to 7 µs execution time (F0830, F083A and F1680 series). VDD = 2. 7 to 3. 6V TA = - 40ºC to +105ºC Parameter NVDS Byte Read Time NVDS Byte Program Time Data Retention Endurance Min 71 126 10 100, 000 Typ Max 256 136 Units µs µs years Cycles Notes With system clock at 20 MHz With system clock at 20 MHz 25ºC Cumulative write cycles for entire memory Table 7. F0830 and F083A NVDS timing values AN031001-0710 Page 4 of 9 NVDS Operation in the Z8 Encore!® and Z8 Encore!XP® MCU's Application Note VDD = 2. 7 to 3. 6V TA = 0ºC to +70ºC TA = - 40ºC to +105ºC Parameter NVDS Byte Read Time NVDS Byte Program Time Data Retention Endurance Min 34 0. 171 20 50, 000 Typ Max 519 39. 7 Units µs ms years cycles Notes With system clock at 20 MHz With system clock at 20 MHz 25ºC Cumulative write cycles for entire memory Table 8. F1680 NVDS timing values NVDS Read Operation Steps in reading a byte from the NVDS array: 1. Pop the address off the stack At the return from the sub-routine, the read byte resides in working register R0, and the read status byte resides in working register R1. The bit fields of this status byte are defined in Table 6 and Table 9. The read routine uses 9 bytes (F082A series) to 16 bytes (F0830, F083A and F1680 series) of stack space in addition to the 1 byte of address pushed by the user. Table 9. Read Status Byte (F0830, F083A and F1680 series) Because of the Flash memory architecture, NVDS reads exhibit a non-uniform execution time. A read operation takes 71 µs - 258 µs (F0830, F083A and F1680 series) or 44 µs - 489 µs (F082A series) for a system clock of 20 MHz. Slower system clock speeds result in proportionally higher execution times. NVDS byte reads from invalid addresses (those exceeding the NVDS array size) return 0xFF. Illegal read operations have an execution time of 2 µs (F082A series) to 6 µs (F0830, F0383A and F1680 series). The status byte returned by the NVDS read routine is 0x00 for successful read. If the status byte is non-zero, there is a corrupted value in the NVDS array at the location being read. In this case, the value returned in R0 is the byte most recently written to the array that does not have an error. AN031001-0710 Page 5 of 9 NVDS Operation in the Z8 Encore!® and Z8 Encore!XP® MCU's Application Note VDD = 2. 7 to 3. 6V TA = - 40ºC to +105ºC Parameter NVDS Byte Read Time NVDS Byte Program Time Data Retention Endurance Min 34 0. 171 100 160, 000 Typ Max 519 39. 7 Units µs ms years cycles Notes With system clock at 20 MHz With system clock at 20 MHz 25ºC Cumulative write cycles for entire memory Table 10. F082A NVDS timing values AN031001-0710 Page 6 of 9 NVDS Operation in the Z8 Encore!® and Z8 Encore!XP® MCU's Application Note Power Failure Protection The NVDS routines employ error checking mechanisms to ensure a power failure endangers only the most recently written byte. For this protection to function, the VBO must be enabled and configured for a threshold voltage of 2. 4 V or greater. [. . . ] XP NVDS can be used for data-logging applications, wherein data needs to be preserved even after power-off. Flowchart AN031001-0710 Page 8 of 9 NVDS Operation in the Z8 Encore!® and Z8 Encore!XP® MCU's Application Note Warning: DO NOT USE IN LIFE SUPPORT LIFE SUPPORT POLICY ZILOG'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF ZILOG CORPORATION. As used herein Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user. A critical component is any component in a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness. Document Disclaimer ©2010 by Zilog, Inc. [. . . ]