User manual YAMAHA YSS912

[. . . ] (Group-A Dolby Digital decoder) No external memory is required (Memory for center and surround channel delay is included) when DTS decoding as well as AC-3 / Pro Logic. Original compression mode as well as four compression modes recommended by Dolby. Pro Logic decoding for Dolby digital 2 channels decoded signal as well as ordinary PCM. High performance 25 MIPS programmable DSP suitable for a variety of sound field processing such as original surround , filtering, virtual surround etc. [. . . ] Clocks XI, XO, CPO The crystal oscillation circuit is formed by using XI and XO terminals. Connect an external analog filter between CPO terminal and Ground. 2. Data Interface SDIA0, SDIA1, SDOA0-2, SDIB0-3, SDOB0-3, SDWCK0, SDBCK0, SDWCK1, SDBCK1, /SDBCK0 Main DSP section AC-3/PCM/DTS data should be fed from SDIA0 or SDIA1 terminal. These signals are processed by AC-3/Pro Logic/DTS decoding procedure in Main DSP section and then transmitted to Sub DSP section as well as outputted through SDOA0-2 terminals. Sub DSP section In Sub DSP section, various types of processing can be applied to the PCM data decoded in Main DSP section or inputted through SDIB0 - 3 terminals. Following parameters can be selected by changing the control register setting. Selection of Main DSP input signal (SDIA0, SDIA1) Selection of Sub DSP input signal (Main DSP output, SDIB0-3 input) Polarity of bit clock and word clock Format and bit count of input/output data For more information on the format of the input/output data, please refer to "Serial Data Interface" section. . Microprocessor Interface /CS, /CSB, SCK, SI, SO The control registers can be read/written via the serial microprocessor interface by using /CS, SCK, SI, and SO terminals. Please refer to the following format diagram for the details of read/write timing. 6 YSS912 Format diagram for read/write timing When /CS=1, the SO output becomes high-impedance. * Be sure to set /CSB to "1" when making an access to the control register. The sound field processing program used for Sub DSP is down-loaded by using the /CSB, SCK, and SI terminals. External Interface RAMA0-16, RAMD0-7, RAMCEN, RAMOEN, RAMWEN An external SRAM can be connected to Sub DSP. 5. General purpose I/O ports OPORT0-7, IPORT0-7 OPORT0-7 terminals are output ports for general purpose. Data written on the register (address 0x04) are outputted from these terminals. Data inputted to these terminals can be read from the register (address 0x05). 6. Initial clear /IC This LSI requires initial clear when turning on the power. 7. LSI test terminals TEST Leave the test terminals open in normal use. 7 YSS912 CONTROL REGISTER The decoding system is controlled by reading and writing the control registers through microprocessor interface (/CS, SCK, SI and SO). 3) When input signal is PCM The contents of registers of address 0x18 to 0x2A are undefined. From the registers of address 0x2D to 0x2F, the following data can be read. address Name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x2D 0x2E 0x2F Pc4 - 0 Pc Register undefined Data Stream Register STREAM7 STREAM6 STREAM5 STREAM4 STREAM3 STREAM2 STREAM1 STREAM0 DTSDATA AC3DATA 2/0MODE SURENC KARAOKE MUTE CRC NONPCM Status Register Address 0x06 to 0x08 and 0x37 to 0x7F are assigned for TEST. Please refer to Application manual for details of Control register. 9 YSS912 SERIAL DATA INTERFACE Data timing of the serial data interface is as follows. Please refer to Application manual for details of SDIA, SDOA, SDIB, and SDOB registers. 10 YSS912 ELECTRICAL CHARACTERISTICS 1. [. . . ] YAMAHA MAKES NO WARRANTY OR REPRESENTATION THAT THE PRODUCTS ARE SUBJECT TO INTELLECTUAL PROPERTY LICENSE FROM YAMAHA OR ANYTHIRD PARTY, AND YAMAHA MAKES NO WARRANTY OR REPRESENTATION OF N ON -IN F R IN GE M E N T W IT H R E S P E C T T O T H E P R OD U C T S . Y A MA H A SPECIFICALLY EXCLUDES ANY LIABILITY TO THE CUSTOMER OR ANY THIRD PARTY ARISING FROM OR RELATED TO THE PRODUCTS' INFRINGEMENT OF ANY THIRD PARTY'S INTELLECTUAL PROPERTY RIGHTS, INCLUDING THE PATENT, COPYRIGHT, TRADEMARK OR TRADE SECRET RIGHTS OF ANY THIRD PARTY. EXAMPLES OF USE DESCRIBED HEREIN ARE MERELY TO INDICATE THE CHARACTERISTICS AND PERFORMANCE OF YAMAHA PRODUCTS. YAMAHA ASSUMES NO RESPONSIBILITY FOR ANY INTELLECTUAL PROPERTY CLAIMS OR OTHER PROBLEMS THAT MAY RESULT FROM APPLICATIONS BASED ON THE EXA MP LE S DES CR IB ED HE RE IN . [. . . ]