User manual TYAN THUNDER 2 ATX

[. . . ] Notice for the USA Compliance Information Statement (Declaration of Conformity Procedure) DoC FCC Part 15: This Device complies with Part 15 of the FCC Rules. Operation is subject to the following conditions: 1) this device may not cause harmful interference, and 2) this device must accept any interference received including interference that may cause undesired operation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try one or more of the following measures: · Reorient or relocate the receiving antenna. · Plug the equipment into an outlet on a circuit different from that of the receiver. [. . . ] CPU Microcode Update Set this option to Enabled to permit the BIOS to update the CPU at any time. Internal Cache This option sets the type of caching algorithm used by the L1 internal cache memory on the CPU. The Optimal and Fail-Safe default settings are Disabled. 38 System BIOS Cacheable When set to Enabled, the contents of the F0000h system memory segment can be read from or written to cache memory. The contents of this memory segment are always copied from the BIOS ROM to system RAM for faster execution. C000, 16K Shadow and C400, 16K Shadow These options specify how the 32 KB of video ROM at C0000h is treated. The settings are: Setting Disabled Enabled Cached Description The contents of the video ROM are not copied to RAM. The contents of the video ROM area from C000h-C7FFFh are copied (shadowed) from ROM to RAM for faster execution. The contents of the video ROM area from C000h-C7FFFh are copied from ROM to RAM and can be written to or read from cache memory. BIOS The Optimal and Fail-Safe default settings are Cached. C800, 16K Shadow; CC00, 16K Shadow; D000, 16K Shadow; D400, 16K Shadow; D800, 16K Shadow; and DC00, 16K Shadow These options enable shadowing of the contents of the ROM area named in the option. The ROM area not used by ISA adapter cards is allocated to PCI adapter cards. The settings are: Setting Disabled Enabled Cached Description The contents of the video ROM are not copied to RAM. The contents of the video ROM area from C000h-C7FFFh are copied (shadowed) from ROM to RAM for faster execution. The contents of the video ROM area from C000h-C7FFFh are copied from ROM to RAM and can be written to or read from cache memory. The Optimal and Fail-Safe default settings are Cached. 39 Chapter 4 Chipset Setup Choose Chipset Setup on the AMIBIOS Setup main menu. USB Function Set this option to Enabled to enable USB (Universal Serial Bus) support. USB Keyboard/Mouse Legacy Support Set this option to Enabled to enable support for older keyboards and mouse devices if the USB Function option is set to Enabled. EDO DRAM Speed (ns) This option specifies the RAS Access Time in nanoseconds for the EDO DRAM system memory installed in this computer. The settings are Auto (AMIBIOS automatically determines the RAS access Time parameter), Manual, 50, 60, or 70. EDO Read Burst Timing This option specifies the timings for EDO DRAM system memory for Read operations in burst mode. EDO Write Burst Timing This option specifies the timings for EDO DRAM system memory for Write operations in burst mode. Setting this switch incorrectly may result in system failure. 40 EDO RAS Precharge This option specifies the length of the RAS precharge part of the DRAM system memory access cycle when EDO DRAM system memory is installed in this computer. EDO RAS To CAS This option specifies the length of the delay inserted between the RAS and CAS signals of the DRAM system memory access cycle when EDO DRAM system memory is installed in this computer. MA Wait State This option specifies the length of the delay inserted between MA signals. [. . . ] If AMIBIOS POST can initialize the system video display, it displays the error message. Displayed error messages, in most cases, allow the system to continue to boot. See the top of the next page for the beep code chart. 68 Beeps 1 2 3 4 5 6 7 8 9 10 11 Error Message Refresh Failure Parity Error Base 64 KB Memory Failure Timer Not Operational Processor Error 8042 - Gate A20 Failure Processor Exception Interrupt Error Display Memory Read/Write Error ROM Checksum Error CMOS Shutdown Register Read/Write Error Cache Memory Bad -- Do Not Enable Cache Description The memory refresh circuitry is faulty. A memory failure in the first 64 KB of memory, or Timer 1 is not functioning. [. . . ]