User manual TRANSCEND TS8GJFT3K

[. . . ] For proper operation in older hosts: while DMA operations are not active, the card shall ignore this signal, including a floating condition 7) Signal usage in True IDE Mode except when Ultra DMA mode protocol is active. 8) Signal usage in True IDE Mode when Ultra DMA mode protocol DMA Write is active. 9) Signal usage in True IDE Mode when Ultra DMA mode protocol DMA Read is active. 10) Signal usage in PC Card I/O and Memory Mode when Ultra DMA mode protocol DMA Write is active. [. . . ] This includes describing the power requirements, IO requirements, memory requirements, manufacturer information and details about the services provided. Table: Sample Device Info Tuple Information for Extended Speeds Note: The value "1" defined for D3 of the N+0 words indicates that no write-protect switch controls writing the ATA registers. The value "0" defined for D7 in the N+2 words indicates that there is not more than a single speed extension byte. Transcend Information Inc. 46 V1. 0 TS4G~32GCF150 TS4G~32GCF150 CF-ATA Drive Register Set Definition and Protocol 150X CompactFlash Card The CompactFlash Storage Card can be configured as a high performance I/O device through: a) The standard PC-AT disk I/O address spaces 1F0h-1F7h, 3F6h-3F7h (primary) or 170h- 177h, 376h-377h (secondary) with IRQ 14 (or other available IRQ). The communication to or from the CompactFlash Storage Card is done using the Task File registers, which provide all the necessary registers for control and status information related to the storage medium. The PCMCIA interface connects peripherals to the host using four register mapping methods. Table 39 is a detailed description of these methods: Transcend Information Inc. 47 V1. 0 TS4G~32GCF150 TS4G~32GCF150 I/O Primary and Secondary Address Configurations Table: Primary and Secondary I/O Decoding 150X CompactFlash Card Transcend Information Inc. 48 V1. 0 TS4G~32GCF150 TS4G~32GCF150 Contiguous I/O Mapped Addressing 150X CompactFlash Card When the system decodes a contiguous block of I/O registers to select the CompactFlash Storage Card, the registers are accessed in the block of I/O space decoded by the system as follows: Table: Contiguous I/O Decoding Transcend Information Inc. 49 V1. 0 TS4G~32GCF150 TS4G~32GCF150 Memory Mapped Addressing 150X CompactFlash Card When the CompactFlash Storage Card registers are accessed via memory references, the registers appear in the common memory space window: 0-2K bytes as follows: True IDE Mode Addressing When the CompactFlash Storage Card is configured in the True IDE Mode, the I/O decoding is as follows: Transcend Information Inc. 50 V1. 0 TS4G~32GCF150 TS4G~32GCF150 CF-ATA Registers 150X CompactFlash Card The following section describes the hardware registers used by the host software to issue commands to the CompactFlash device. These registers are often collectively referred to as the "task file. " Data Register (Address - 1F0h[170h];Offset 0, 8, 9) The Data Register is a 16 bit register, and it is used to transfer data blocks between the CompactFlash Storage Card data buffer and the Host. This register overlaps the Error Register. Error Register (Address - 1F1h[171h]; Offset 1, 0Dh Read Only) This register contains additional information about the source of an error when an error is indicated in bit 0 of the Status register. This register is also accessed in PC Card Modes on data bits D15-D8 during a read operation to offset 0 with -CE2 low and -CE1 high. This bit is also set when an interface CRC error is detected in True IDE Ultra DMA modes of operation. Bit 6 (UNC): this bit is set when an Uncorrectable Error is encountered. Bit 2 (Abort) This bit is set if the command has been aborted because of a CompactFlash Storage Card status condition: (Not Ready, Write Fault, etc. ) or when an invalid command has been issued. During the data transfer of DMA commands, the Card shall not assert DMARQ unless either the BUSY bit, the DRQ bit, or both are set to one. Bit 6 (RDY): RDY indicates whether the device is capable of performing CompactFlash Storage Card operations. This bit is cleared at power up and remains cleared until the CompactFlash Storage Card is ready to accept a command. Bit 4 (DSC): This bit is set when the CompactFlash Storage Card is ready. Bit 3 (DRQ): The Data Request is set when the CompactFlash Storage Card requires that information be transferred either to or from the host through the Data register. During the data transfer of DMA commands, the Card shall not assert DMARQ unless either the BUSY bit, the DRQ bit, or both are set to one. Bit 2 (CORR): This bit is set when a Correctable data error has been encountered and the data has been corrected. Bit 0 (ERR): This bit is set when the previous command has ended in some type of error. The bits in the Error register contain additional information describing the error. It is recommended that media access commands (such as Read Sectors and Write Sectors) that end with an error condition should have the address of the first sector in error in the command block registers. Transcend Information Inc. 53 V1. 0 TS4G~32GCF150 TS4G~32GCF150 Device Control Register (Address - 3F6h[376h]; Offset Eh) 150X CompactFlash Card This register is used to control the CompactFlash Storage Card interrupt request and to issue an ATA soft reset to the card. The bits are defined as follows: Bit 7: this bit is ignored by the CompactFlash Storage Card. [. . . ] Bits 2-0: Maximum Advanced PCMCIA I/O Mode Support Indicates the maximum I/O timing mode supported by the card. Value 0 1 2 3 4-7 Maximum PCMCIA IO timing mode Supported 255ns Cycle PCMCIA I/O Mode 120ns Cycle PCMCIA I/O Mode 100ns Cycle PCMCIA I/O Mode 80ns Cycle PCMCIA I/O Mode Reserved Bits 5-3: Maximum Memory timing mode supported Indicates the Maximum Memory timing mode supported by the card. Value Maximum Memory timing mode Supported 0 250ns Cycle Memory Mode 1 120ns Cycle Memory Mode 2 100ns Cycle Memory Mode 3 80ns Cycle Memory Mode 4-7 Reserved Transcend Information Inc. 69 V1. 0 TS4G~32GCF150 TS4G~32GCF150 150X CompactFlash Card Bits 8-6: Maximum PC Card I/O UDMA timing mode supported Indicates the Maximum PC Card I/O UDMA timing mode supported by the card when bit 15 is set. Value 0 1 2 3 4 5 6 7 Maximum PC Card I/O UDMA timing mode Supported PC Card I/O UDMA mode 0 supported PC Card I/O UDMA mode 1 supported PC Card I/O UDMA mode 2 supported PC Card I/O UDMA mode 3 supported PC Card I/O UDMA mode 4 supported PC Card I/O UDMA mode 5 supported Reserved Reserved Bits 11-9: Maximum PC Card Memory UDMA timing mode supported Indicates the Maximum PC Card Memory UDMA timing mode supported by the card when bit 15 is set. [. . . ]