User manual TRANSCEND TS64GJFV20

DON'T FORGET : ALWAYS READ THE USER GUIDE BEFORE BUYING !!!

If this document matches the user guide, instructions manual or user manual, feature sets, schematics you are looking for, download it now. Diplodocs provides you a fast and easy access to the user manual TRANSCEND TS64GJFV20. We hope that this TRANSCEND TS64GJFV20 user guide will be useful to you.


TRANSCEND TS64GJFV20 : Download the complete user guide (1196 Ko)

You may also download the following manuals related to this product:

   TRANSCEND TS64GJFV20 (1136 ko)
   TRANSCEND TS64GJFV20 (1426 ko)
   TRANSCEND TS64GJFV20 (1233 ko)
   TRANSCEND TS64GJFV20 (1014 ko)
   TRANSCEND TS64GJFV20 (1346 ko)
   TRANSCEND TS64GJFV20 (957 ko)
   TRANSCEND TS64GJFV20 (986 ko)
   TRANSCEND TS64GJFV20 (1539 ko)
   TRANSCEND TS64GJFV20 (1133 ko)
   TRANSCEND TS64GJFV20 (1282 ko)
   TRANSCEND TS64GJFV20 (1152 ko)
   TRANSCEND TS64GJFV20 (1210 ko)
   TRANSCEND TS64GJFV20 (1106 ko)
   TRANSCEND TS64GJFV20 (1277 ko)
   TRANSCEND TS64GJFV20 DATASHEET (107 ko)

Manual abstract: user guide TRANSCEND TS64GJFV20

Detailed instructions for use are in the User's Guide.

[. . . ] In these modes, the pin should be connected by the host to PC Card A25 or grounded by the host. 6) If DMA operations are not used, the signal should be held high or tied to VCC by the host. For proper operation in older hosts: while DMA operations are not active, the card shall ignore this signal, including a floating condition 7) Signal usage in True IDE Mode except when Ultra DMA mode protocol is active. 8) Signal usage in True IDE Mode when Ultra DMA mode protocol DMA Write is active. [. . . ] The host shall not configure a card into Ultra DMA mode when a card not supporting Ultra DMA is also present on the same interface When the use of two cards on an interface is otherwise permitted, the host may use any mode that is supported by both cards, but to achieve maximum performance it should use its highest performance mode that is also supported by both cards. Metaformat Overview The goal of the Metaformat is to describe the requirements and capabilities of the CompactFlash Storage Card as thoroughly as possible. This includes describing the power requirements, IO requirements, memory requirements, manufacturer information and details about the services provided. Table: Sample Device Info Tuple Information for Extended Speeds Note: The value "1" defined for D3 of the N+0 words indicates that no write-protect switch controls writing the ATA registers. The value "0" defined for D7 in the N+2 words indicates that there is not more than a single speed extension byte. Transcend Information Inc. 49 V1. 4 TS8G~64GCF400 TS8G~64GCF400 CF-ATA Drive Register Set Definition and Protocol 400X CompactFlash Card The CompactFlash Storage Card can be configured as a high performance I/O device through: a) The standard PC-AT disk I/O address spaces 1F0h-1F7h, 3F6h-3F7h (primary) or 170h- 177h, 376h-377h (secondary) with IRQ 14 (or other available IRQ). The communication to or from the CompactFlash Storage Card is done using the Task File registers, which provide all the necessary registers for control and status information related to the storage medium. The PCMCIA interface connects peripherals to the host using four register mapping methods. Table 39 is a detailed description of these methods: Transcend Information Inc. 50 V1. 4 TS8G~64GCF400 TS8G~64GCF400 I/O Primary and Secondary Address Configurations Table: Primary and Secondary I/O Decoding 400X CompactFlash Card Transcend Information Inc. 51 V1. 4 TS8G~64GCF400 TS8G~64GCF400 Contiguous I/O Mapped Addressing 400X CompactFlash Card When the system decodes a contiguous block of I/O registers to select the CompactFlash Storage Card, the registers are accessed in the block of I/O space decoded by the system as follows: Table: Contiguous I/O Decoding Transcend Information Inc. 52 V1. 4 TS8G~64GCF400 TS8G~64GCF400 Memory Mapped Addressing 400X CompactFlash Card When the CompactFlash Storage Card registers are accessed via memory references, the registers appear in the common memory space window: 0-2K bytes as follows: True IDE Mode Addressing When the CompactFlash Storage Card is configured in the True IDE Mode, the I/O decoding is as follows: Transcend Information Inc. 53 V1. 4 TS8G~64GCF400 TS8G~64GCF400 CF-ATA Registers 400X CompactFlash Card The following section describes the hardware registers used by the host software to issue commands to the CompactFlash device. These registers are often collectively referred to as the "task file. " Data Register (Address - 1F0h[170h];Offset 0, 8, 9) The Data Register is a 16 bit register, and it is used to transfer data blocks between the CompactFlash Storage Card data buffer and the Host. This register overlaps the Error Register. Error Register (Address - 1F1h[171h]; Offset 1, 0Dh Read Only) This register contains additional information about the source of an error when an error is indicated in bit 0 of the Status register. This register is also accessed in PC Card Modes on data bits D15-D8 during a read operation to offset 0 with -CE2 low and -CE1 high. This bit is also set when an interface CRC error is detected in True IDE Ultra DMA modes of operation. Bit 6 (UNC): this bit is set when an Uncorrectable Error is encountered. Reading the Status register does clear a pending interrupt while reading the Auxiliary Status register does not. The status bits are described as follows: Bit 7 (BUSY): the busy bit is set when the CompactFlash Storage Card has access to the command buffer and registers and the host is locked out from accessing the command register and buffer. During the data transfer of DMA commands, the Card shall not assert DMARQ unless either the BUSY bit, the DRQ bit, or both are set to one. Bit 6 (RDY): RDY indicates whether the device is capable of performing CompactFlash Storage Card operations. This bit is cleared at power up and remains cleared until the CompactFlash Storage Card is ready to accept a command. Bit 4 (DSC): This bit is set when the CompactFlash Storage Card is ready. Bit 3 (DRQ): The Data Request is set when the CompactFlash Storage Card requires that information be transferred either to or from the host through the Data register. During the data transfer of DMA commands, the Card shall not assert DMARQ unless either the BUSY bit, the DRQ bit, or both are set to one. Bit 2 (CORR): This bit is set when a Correctable data error has been encountered and the data has been corrected. Bit 0 (ERR): This bit is set when the previous command has ended in some type of error. The bits in the Error register contain additional information describing the error. [. . . ] Word 164: CF Advanced PCMCIA I/O and Memory Timing Modes Capabilities and Settings This word describes the capabilities and current settings for CFA defined advanced timing modes using the Memory and PCMCIA I/O interface. Notice: The use of PCMCIA I/O or Memory modes that are 100ns or faster impose significant restrictions on the implementation of the host: Additional Requirements for CF Advanced Timing Modes. Bits 2-0: Maximum Advanced PCMCIA I/O Mode Support Indicates the maximum I/O timing mode supported by the card. Value 0 1 2 3 4-7 Maximum PCMCIA IO timing mode Supported 255ns Cycle PCMCIA I/O Mode 120ns Cycle PCMCIA I/O Mode 100ns Cycle PCMCIA I/O Mode 80ns Cycle PCMCIA I/O Mode Reserved Bits 5-3: Maximum Memory timing mode supported Indicates the Maximum Memory timing mode supported by the card. [. . . ]

DISCLAIMER TO DOWNLOAD THE USER GUIDE TRANSCEND TS64GJFV20




Click on "Download the user Manual" at the end of this Contract if you accept its terms, the downloading of the manual TRANSCEND TS64GJFV20 will begin.

 

Copyright © 2015 - manualRetreiver - All Rights Reserved.
Designated trademarks and brands are the property of their respective owners.