User manual TRANSCEND TS512MJFV20

[. . . ] The maximum load on -IOCS16 is 1 LSTTL with a 50 pF (40pF below 120nsec Cycle Time) total load. Minimum time from -IORDY high to -IORD high is 0 nsec, but minimum -IORD width shall still be met. (1) t0 is the minimum total cycle time, t2 is the minimum command active time, and t2i is the minimum command recovery time or command inactive time. The actual cycle time equals the sum of the actual command active time and the actual command inactive time. [. . . ] The following steps shall occur in the order they are listed unless otherwise specifically allowed: (a) The host shall not pause an Ultra DMA data burst until at least one data word of an Ultra DMA data burst has been transferred. (b) The host shall pause an Ultra DMA data burst by negating -HDMARDY. (c) The device shall stop generating DSTROBE edges within tRFS of the host negating -HDMARDY. (d) While operating in Ultra DMA modes 2, 1, or 0 the host shall be prepared to receive zero, one or two additional data words after negating -HDMARDY. While operating in Ultra DMA modes 4 or 3 the host shall be prepared to receive zero, one, two or three additional data words. The additional data words are a result of cable round trip delay and tRFS timing for the device. (e) The host shall resume an Ultra DMA data burst by asserting -HDMARDY. ALL WAVEFORMS IN THIS DIAGRAM ARE SHOWN WITH THE ASSERTED STATE HIGH. NEGATIVE TRUE SIGNALS APPEAR INVERTED ON THE BUS RELATIVE TO THE DIAGRAM. Notes: (1) The host may assert STOP to request termination of the Ultra DMA data burst no sooner than tRP after -HDMARDY is negated. (2) After negating -HDMARDY, the host may receive zero, one, two, or three more data words from the device. (3) The bus polarity of the (-) DMARQ and (-)DMACK signals is dependent on the active interface mode. Transcend Information Inc. 19 Ver 1. 2 Transcend 44-Piin IIDE Fllash Modulle Transcend 44-P n DE F ash Modu e TS128M ~ 8GDOM44V-S TS128M ~ 8GDOM44V-S Device Terminating an Ultra DMA Data-In Burst The device terminates an Ultra DMA Data-In burst by following the steps lettered below. (g) If DSTROBE is negated, the device shall assert DSTROBE within tLI after the host has asserted STOP. DSTROBE shall remain asserted until the Ultra DMA data burst is terminated. (h) The device shall release D[15:00] no later than tAZ after negating DMARQ. (i) The host shall drive D[15:00] no sooner than tZAH after the device has negated DMARQ. For this step, the host may first drive D[15:00] with the result of its CRC calculation (see ATA specification Ultra DMA CRC Calculation). (j) If the host has not placed the result of its CRC calculation on D[15:00] since first driving D[15:00] during (9), the host shall place the result of its CRC calculation on D[15:00] (see ATA specification Ultra DMA CRC Calculation). (k) The host shall negate -DMACK no sooner than tMLI after the device has asserted DSTROBE and negated DMARQ and the host has asserted STOP and negated -HDMARDY, and no sooner than tDVS after the host places the result of its CRC calculation on D[15:00]. (l) The device shall latch the host's CRC data from D[15:00] on the negating edge of -DMACK. (m) The device shall compare the CRC data received from the host with the results of its own CRC calculation. If a miscompare error occurs during one or more Ultra DMA data burst for any one command, at the end of the command, the device shall report the first error that occurred (see ATA specification Ultra DMA CRC Calculation) (n) While operating in True IDE mode, the device shall release DSTROBE within tIORDYZ after the host negates -DMACK. (o) The host shall neither negate STOP nor assert -HDMARDY until at least tACK after the host has negated -DMACK. [. . . ] (c) The device shall negate DMARQ within tLI after the host asserts STOP. The device shall not assert DMARQ again until after the Ultra DMA data burst is terminated. (d) The device shall negate -DDMARDY within tLI after the host has negated STOP. The device shall not assert -DDMARDY again until after the Ultra DMA data burst termination is complete. [. . . ]