User manual TRANSCEND TS16GJFV30

[. . . ] If Pin 20 of the IDE connector is defined as VCC, then the 40-Pin IDE Flash Module can get necessary power without use of the power cord. 01 -RESET 11 02 GND 12 03 04 05 06 07 08 09 10 HD7 HD8 HD6 HD9 HD5 HD10 HD4 HD11 13 14 15 16 17 18 19 20 21 DMARQ 31 22 GND 32 23 24 25 26 27 28 30 IOWB GND IORB GND IORDY NC GND 33 34 35 36 37 38 40 29 -DMACK 39 Pin Definition Symbol HD0 ~ HD15 HA0 ~ HA2 -RESET IORB IOWB IOIS16B CE1B, CE2B PDIAGB DASPB DMARQ DMACKIREQ NC GND VCC Pin Layout Function Pin1 Data Bus (Bi-directional) Address Bus (Input) Device Reset (Input) Device I/O Read (Input) Device I/O Write (Input) Transfer Type 8/16 bit (Output) Chip Select (Input) Pass Diagnostic (Bi-directional) Disk Active/Slave Present (Bi-directional) DMA request DMA acknowledge Interrupt Request (Output) No Connection Ground Vcc Power Input Bulge Pin39 Pin2 Pin40 Transcend Information Inc. 2 Ver 1. 2 Transcend 40-Piin IIDE Fllash Modulle Transcend 40-P n DE F ash Modu e TS128M ~ 16GDOM40V-S TS128M ~ 16GDOM40V-S Block Diagram With 1 pcs of Flash Memory: With 2 pcs of Flash Memory: Transcend Information Inc. 3 Ver 1. 2 Transcend 40-Piin IIDE Fllash Modulle Transcend 40-P n DE F ash Modu e TS128M ~ 16GDOM40V-S TS128M ~ 16GDOM40V-S Ratings Absolute Maximum Ratings Symbol VDD-VSS Ta Tst Parameter DC Power Supply Operating Temperature Storage Temperature Min -0. 6 0 -40 Max +6 +70 +85 Unit V °C °C Recommended Operating Conditions Symbol VDD VIN Ta Parameter Power supply Input voltage Operating Temperature Min 3. 0 0 0 Max 5. 5 VDD+0. 3 +70 Units V V °C DC Characteristics (Ta=0 C to +70 C, Vcc = 5. 0V ±10%) Parameter Supply Voltage High level output voltage Low level output voltage High level input voltage Low level input voltage o o o o Symbol VCC VOH VOL VIH VIL Min 4. 5 VCC-0. 8 -4. 0 2. 92 --- Max 5. 5 -0. 8 --0. 8 1. 70 Unit V V V V V V V Remark Non-schmitt trigger Schmitt trigger Schmitt trigger 1 Non-schmitt trigger 1 (Ta=0 C to +70 C, Vcc = 3. 3V ±5%) Parameter Supply Voltage High level output voltage Low level output voltage High level input voltage Low level input voltage Symbol VCC VOH VOL VIH VIL Min 3. 135 VCC-0. 8 -2. 4 2. 05 --- Max 3. 465 -0. 8 --0. 6 1. 25 Unit V V V V V V V Remark Non-schmitt trigger Schmitt trigger Schmitt trigger 1 Non-schmitt trigger 1 Transcend Information Inc. 4 Ver 1. 2 Transcend 40-Piin IIDE Fllash Modulle Transcend 40-P n DE F ash Modu e TS128M ~ 16GDOM40V-S TS128M ~ 16GDOM40V-S Transcend Information Inc. 5 Ver 1. 2 Transcend 40-Piin IIDE Fllash Modulle Transcend 40-P n DE F ash Modu e TS128M ~ 16GDOM40V-S TS128M ~ 16GDOM40V-S True IDE PIO Mode Read/Write Timing Mode Mode Mode Mode Mode Mode Mode 0 1 2 3 4 5 6 1 t0 Cycle time (min) 600 383 240 180 120 100 80 t1 Address Valid to -IORD/-IOWR setup (min) 70 50 30 30 25 15 10 1 t2 -IORD/-IOWR (min) 165 125 100 80 70 65 55 t2 -IORD/-IOWR (min) Register (8 bit) 290 290 290 80 70 65 55 t2i -IORD/-IOWR recovery time (min) ---70 25 25 20 t3 -IOWR data setup (min) 60 45 30 30 20 20 15 t4 -IOWR data hold (min) 30 20 15 10 10 5 5 t5 -IORD data setup (min) 50 35 20 20 20 15 10 t6 -IORD data hold (min) 5 5 5 5 5 5 5 2 t6Z -IORD data tristate (max) 30 30 30 30 30 20 20 4 t7 Address valid to IOCS16 assertion (max) 90 50 40 N/A N/A N/A N/A 4 t8 Address valid to IOCS16 released (max) 60 45 30 N/A N/A N/A N/A t9 -IORD/-IOWR to address valid hold 20 15 10 10 10 10 10 tRD Read Data Valid to IORDY active (min), if 0 0 0 0 0 0 0 IORDY initially low after tA 5 5 tA IORDY Setup time 3 35 35 35 35 35 N/A N/A 5 5 tB IORDY Pulse Width (max) 1250 1250 1250 1250 1250 N/A N/A 5 5 tC IORDY assertion to release (max) 5 5 5 5 5 N/A N/A Notes: All timings are in nanoseconds. The maximum load on -IOCS16 is 1 LSTTL with a 50 pF (40pF below 120nsec Cycle Time) total load. Minimum time from -IORDY high to -IORD high is 0 nsec, but minimum -IORD width shall still be met. Item (1) t0 is the minimum total cycle time, t2 is the minimum command active time, and t2i is the minimum command recovery time or command inactive time. [. . . ] A timing diagram is shown in below: Ultra DMA Data-In Burst Host Pause Timing. The timing parameters are specified in Page 12: Ultra DMA Data Burst Timing Requirements and are described in Page 13: Ultra DMA Data Burst Timing Descriptions. The following steps shall occur in the order they are listed unless otherwise specifically allowed: (a) The host shall not pause an Ultra DMA data burst until at least one data word of an Ultra DMA data burst has been transferred. (b) The host shall pause an Ultra DMA data burst by negating -HDMARDY. (c) The device shall stop generating DSTROBE edges within tRFS of the host negating -HDMARDY. (d) While operating in Ultra DMA modes 2, 1, or 0 the host shall be prepared to receive zero, one or two additional data words after negating -HDMARDY. While operating in Ultra DMA modes 4 or 3 the host shall be prepared to receive zero, one, two or three additional data words. The additional data words are a result of cable round trip delay and tRFS timing for the device. (e) The host shall resume an Ultra DMA data burst by asserting -HDMARDY. ALL WAVEFORMS IN THIS DIAGRAM ARE SHOWN WITH THE ASSERTED STATE HIGH. NEGATIVE TRUE SIGNALS APPEAR INVERTED ON THE BUS RELATIVE TO THE DIAGRAM. Notes: (1) The host may assert STOP to request termination of the Ultra DMA data burst no sooner than tRP after -HDMARDY is negated. (f) The device shall negate DMARQ within tLI after the host has asserted STOP. The device shall not assert DMARQ again until after the Ultra DMA data burst is terminated. (g) If DSTROBE is negated, the device shall assert DSTROBE within tLI after the host has asserted STOP. DSTROBE shall remain asserted until the Ultra DMA data burst is terminated. (h) The device shall release D[15:00] no later than tAZ after negating DMARQ. (i) The host shall drive D[15:00] no sooner than tZAH after the device has negated DMARQ. For this step, the host may first drive D[15:00] with the result of its CRC calculation (see ATA specification Ultra DMA CRC Calculation). (j) If the host has not placed the result of its CRC calculation on D[15:00] since first driving D[15:00] during (9), the host shall place the result of its CRC calculation on D[15:00] (see ATA specification Ultra DMA CRC Calculation). (k) The host shall negate -DMACK no sooner than tMLI after the device has asserted DSTROBE and negated DMARQ and the host has asserted STOP and negated -HDMARDY, and no sooner than tDVS after the host places the result of its CRC calculation on D[15:00]. (l) The device shall latch the host's CRC data from D[15:00] on the negating edge of -DMACK. (m) The device shall compare the CRC data received from the host with the results of its own CRC calculation. [. . . ] (c) The device shall negate DMARQ within tLI after the host asserts STOP. The device shall not assert DMARQ again until after the Ultra DMA data burst is terminated. (d) The device shall negate -DDMARDY within tLI after the host has negated STOP. The device shall not assert -DDMARDY again until after the Ultra DMA data burst termination is complete. [. . . ]