User manual TEXAS INSTRUMENTS TVP5160 DATA MANUAL REV C

[. . . ] TVP5160 NTSC/PAL/SECAM/Component 2x10-Bit Digital Video Decoder Data Manual PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Literature Number: SLES135C February 2005 ­ Revised May 2010 TVP5160 SLES135C ­ FEBRUARY 2005 ­ REVISED MAY 2010 www. ti. com Contents 1 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1. 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . [. . . ] The proper sequence to change the external sync positions is: · To set NTSC, PAL-M, NTSC 443, PAL 60 (525-line modes): ­ Make sure the standard is one of the above 525-line mode formats by forcing the video standard ­ Set HS, VS, VBLK, and AVID external syncs (register 16h through 24h) · To set PAL, PAL-N, SECAM (625-line modes): ­ Make sure the standard is one of the above 625-line mode formats by forcing the video standard ­ Set HS, VS, VBLK, and AVID external syncs (register 16h through 24h) Once programmed, the values for each mode are retained when the signal switches back into that or other compatible video standards. Copyright © 2005­2010, Texas Instruments Incorporated Functional Description Submit Documentation Feedback Product Folder Link(s): TVP5160 37 TVP5160 SLES135C ­ FEBRUARY 2005 ­ REVISED MAY 2010 www. ti. com 3 Internal Control Registers The TVP5160 decoder is initialized and controlled by a set of internal registers that define the operating parameters of the entire device. Communication between the external controller and the TVP5160 decoder is through a standard I2C host port interface, as described earlier. Detailed programming information for each register is described in the following sections. Additional registers are accessible through an indirect procedure involving access to an internal 24-bit address wide VBUS. I2C Registers Summary REGISTER NAME I2C SUBADDRESS 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h­17h 18h­19h 1Ah­1Bh 1Ch­1Dh 1Eh­1Fh 20h­21h 22h­23h 24h­25h 26h 27h 28h 29h 2Ah 2Bh 55h/5Fh 325h/32Fh 00h/07h 40h/47h 004h/001h 007h/004h 001h/26Fh 015h/018h 00h 00h C0h 17h 1Ch 12h R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 80h R/W 80h 80h 80h R/W R/W R/W DEFAULT 00h 0Fh 00h 00h 23h 10h 00h 00h 00h 80h 80h 80h 00h 00h 0Ch R/W (1) R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Input/Output Select AFE Gain Control Video Standard Select Operation Mode Autoswitch Mask Color Killer Luminance Processing Control 1 Luminance Processing Control 2 Luminance Processing Control 3 Luminance Brightness Luminance Contrast Chrominance Saturation Chroma Hue Chrominance Processing Control 1 Chrominance Processing Control 2 Reserved (2) Pr Contrast Y Contrast Pb Contrast Reserved (2) G/Y Brightness Reserved (2) AVID Start Pixel AVID Stop Pixel HS Start Pixel HS Stop Pixel VS Start Line VS Stop Line VBLK Start Line VBLK Stop Line Embedded Sync Offset Control 1 Embedded Sync Offset Control 2 Fast Switch Control Fast Switch Overlay Delay Fast Switch SCART Delay Overlay Delay (1) (2) 38 R = Read only, W = Write only, R/W = Read and write Reserved I2C register addresses must not be written to. Internal Control Registers Copyright © 2005­2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5160 TVP5160 www. ti. com SLES135C ­ FEBRUARY 2005 ­ REVISED MAY 2010 Table 3-1. I2C Registers Summary (continued) REGISTER NAME SCART Delay Reserved(2) CTI Control Brightness and Contrast Range Extender Component Autoswitch Mask Reserved(2) Sync Control Output Formatter 1 Output Formatter 2 Output Formatter 3 Output Formatter 4 Output Formatter 5 Output Formatter 6 Clear Lost Lock Detect Status 1 Status 2 AGC Gain Status Reserved(2) Video Standard Status GPIO Input 1 GPIO Input 2 Reserved(2) Back End AGC Status Reserved (2) I2C SUBADDRESS 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch­3Dh 3Eh 3Fh 40h 41h 42h-43h 44h 45h 46h 47h 48h 49h 4Ah­4Bh 4Ch­4Dh 4Eh­4Fh 50h­51h 52h-56h 57h 58h 59h 5Ah 5Bh 5Ch 5Dh 5Eh 5Fh 60h 61h 62h 64h 65h DEFAULT 56h 00h 00h 00h 00h 40h 00h FFh FFh FFh FFh 00h R/W (1) R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R R R R AFE Coarse Gain for CH1 AFE Coarse Gain for CH2 AFE Coarse Gain for CH3 AFE Coarse Gain for CH4 AFE Fine Gain for Pb AFE Fine Gain for Chroma AFE Fine Gain for Pr AFE Fine Gain for CVBS_Luma Reserved(2) 656 Version Reserved(2) SDRAM Control Y Noise Sensitivity UV Noise Sensitivity Y coring threshold UV coring threshold Low Noise Limit "Blue" Screen Y "Blue" Screen Cb "Blue" Screen Cr "Blue" Screen LSB 3DNR Noise Measurement LSB 3DNR Noise Measurement MSB 20h 20h 20h 20h 900h 900h 900h 900h 00h 00h 80h 80h 80h 40h 40h 00h 80h 80h 00h R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R Copyright © 2005­2010, Texas Instruments Incorporated Internal Control Registers Submit Documentation Feedback Product Folder Link(s): TVP5160 39 TVP5160 SLES135C ­ FEBRUARY 2005 ­ REVISED MAY 2010 www. ti. com Table 3-1. I2C Registers Summary (continued) REGISTER NAME Y Core0 (3DNR) UV Core0 (3DNR) Reserved(2) F and V Bit Decode Control Reserved(2) Back End AGC Control Reserved (2) I2C SUBADDRESS 66h 67h 68h 69h 6Ah-6Bh 6Ch 6Eh 6Fh 70h 71h-73h 74h 75h 76h-77h 78h 79h 7Fh 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah­8Bh 8Dh 8Eh 8Fh 90h 91h-94h 95h 96h 97h 98h 99h 9Ah­9Bh 9Ch-9Dh 9Eh 9Fh-B0h B1h B2h B3h B4h B5h B6h DEFAULT R/W (1) R R 00h 08h 04h R/W R/W R/W R AGC Decrement Speed ROM Version Reserved(2) AGC White Peak Processing F and V Bit Control Reserved(2) AGC Increment Speed AGC Increment Delay Analog Output Control 1 CHIP ID MSB CHIP ID LSB Reserved(2) Color PLL Speed Control 3DYC Luma Coring LSB 3DYC Chroma Coring LSB 3DYC Chroma/Luma MSBs 3DYC Luma Gain 3DYC Chroma Gain 3DYC Signal Quality Gain 3DYC Signal Quality Coring IF Compensation Control IF Differential Gain Control IF Low Frequency Gain Control IF High Frequency Gain Control Reserved(2) Weak Signal High Threshold Weak Signal Low Threshold Status Request 3DYC NTSC VCR Threshold 3DYC PAL VCR Threshold Vertical Line Count Reserved(2) AGC Decrement Delay Reserved (2) 00h 16h 06h 1Eh 00h 51h 60h 09h 20h/20h 20h/2Ah 00h/00h 08h/08h 08h/08h 02h/02h 328h/380h 00h 22h 44h 00h 60h 50h 00h 10h 20h 00h R/W R/W R/W R/W R/W R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W VDP TTX Filter 1 Mask 1 VDP TTX Filter 1 Mask 2 VDP TTX Filter 1 Mask 3 VDP TTX Filter 1 Mask 4 VDP TTX Filter 1 Mask 5 VDP TTX Filter 2 Mask 1 40 Internal Control Registers 00h 00h 00h 00h 00h 00h R/W R/W R/W R/W R/W R/W Copyright © 2005­2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5160 TVP5160 www. ti. com SLES135C ­ FEBRUARY 2005 ­ REVISED MAY 2010 Table 3-1. I2C Registers Summary (continued) REGISTER NAME VDP TTX Filter 2 Mask 2 VDP TTX Filter 2 Mask 3 VDP TTX Filter 2 Mask 4 VDP TTX Filter 2 Mask 5 VDP TTX Filter Control VDP FIFO Word Count VDP FIFO Interrupt Threshold Reserved VDP FIFO Reset VDP FIFO Output Control VDP Line Number Interrupt VDP Pixel Alignment Reserved VDP Line Start VDP Line Stop VDP Global Line Mode VDP Full Field Enable VDP Full Field Mode Interlaced/Progressive Status Reserved(2) VBUS Data Access with No VBUS Address Increment VBUS Data Access with VBUS Address Increment VDP FIFO Read Data Reserved (2) I2C SUBADDRESS B7h B8h B9h BAh BBh BCh BDh BEh BFh C0h C1h C2h­C3h C4h­D5h D6h D7h D8h D9h DAh DBh DCh-DFh E0h E1h E2h E3h-E7h E8h­EAh EBh-EFh F0h F1h F2h F3h F4h F5h F6h F7h F8h-FFh DEFAULT 00h 00h 00h 00h 00h 80h 00h 00h 00h 01Eh 06h 1Bh FFh 00h FFh R/W (1) R/W R/W R/W W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R VBUS Address Access Reserved(2) Interrupt Raw Status 0 Interrupt Raw Status 1 Interrupt Status 0 Interrupt Status 1 Interrupt Mask 0 Interrupt Mask 1 Interrupt Clear 0 Interrupt Clear 1 Reserved(2) 00 0000h R/W R R R R 00h 00h 00h 00h R/W R/W R/W R/W Copyright © 2005­2010, Texas Instruments Incorporated Internal Control Registers Submit Documentation Feedback Product Folder Link(s): TVP5160 41 TVP5160 SLES135C ­ FEBRUARY 2005 ­ REVISED MAY 2010 www. ti. com Table 3-2. VBUS Registers Summary REGISTER NAME Reserved (2) (3) VBUS SUBADDRESS 00 0000h ­ 80 051Bh 80 051Ch ­ 80 051Fh 80 0520h ­ 80 0526h 80 0527h ­ 80 052Bh 80 052Ch ­ 80 0534h 80 0535h ­ 80 053Fh 80 0540h ­ 80 0543h 80 0544h ­ 80 05FFh 80 0600h ­ 80 0611h 80 0612h ­ 80 06FFh 80 0700h ­ 80 070Ch 80 070Dh ­ A0 005Dh A0 005Eh A0 005Fh ­ B0 005Fh B0 0060h B0 0062h ­ B0 0064h B0 0065h B0 0069h B0 006Dh B0 0071h B0 0073h ­ FF FFFFh DEFAULT R/W (1) R R R R VDP Closed Caption Data VDP WSS/CGMS data Reserved Reserved Reserved Reserved Reserved Reserved Reserved (2) (3) VDP VITC Data (2) (3) VDP V-Chip Data (2) (3) VDP General Line Mode and Address (2) (3) FFh, 00h R/W R VDP VPS/Gemstar EPG Data (2) (3) Analog Output Control 2 (2) (3) B2h 00h R/W R/W R R R R Interrupt Configuration Register (2) (3) Interrupt Mask 1 Interrupt Raw Status 1 Interrupt Status 1 Interrupt Clear 1 Reserved (2) (3) (1) (2) (3) R = Read only, W = Write only, R/W = Read and write Register addresses not shown in the register map summary are reserved and must not be written to. Writing to or reading from any value labeled "Reserved" register may cause erroneous operation of the TVP5160 decoder. For registers with reserved bits, a 0b must be written to reserved bit locations unless otherwise stated. 42 Internal Control Registers Submit Documentation Feedback Product Folder Link(s): TVP5160 Copyright © 2005­2010, Texas Instruments Incorporated TVP5160 www. ti. com SLES135C ­ FEBRUARY 2005 ­ REVISED MAY 2010 3. 1 Register Definitions Table 3-3. Input/Output Select Subaddress Default 7 00h 00h 6 5 4 3 Input select [7:0] 2 1 0 Twelve input terminals can be configured to support composite, S-Video, and component YPbPr. Analog Channel and Video Mode Selection MODE CVBS VI_1 (default) VI_2 VI_3 VI_4 VI_5 VI_6 VI_7 VI_8 VI_9 VI_10 VI_11 VI_12 S-Video VI_1(Y), VI_7(C) VI_2(Y), VI_8(C) VI_3(Y), VI_9(C) VI_1(Y), VI_10(C) VI_2(Y), VI_11(C) VI_3(Y), VI_12(C) VI_4(Y), VI_7(C) VI_5(Y), VI_8(C) VI_6(Y), VI_9(C) VI_4(Y), VI_10(C) VI_5(Y), VI_11(C) VI_6(Y), VI_12(C) YPbPr VI_10(Pb), VI_1(Y), VI_7(Pr) VI_11(Pb), VI_2(Y), VI_8(Pr) VI_12(Pb), VI_3(Y), VI_9(Pr) VI_10(Pb), VI_4(Y), VI_7(Pr) VI_11(Pb), VI_5(Y), VI_8(Pr) VI_12(Pb), VI_6(Y), VI_9(Pr) SCART VI_10(B), VI_4(G), VI_7(R), VI_1(CVBS) VI_11(B), VI_5(G), VI_8(R), VI_2(CVBS) VI_12(B), VI_6(G), VI_9(R), VI_3(CVBS) INPUT(S) SELECTED INPUT SELECT [7:0] 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 6 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 1 1 1 1 1 1 1 1 0 0 0 3 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 1 1 1 0 0 0 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 1 1 1 0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 HEX 00 01 02 04 05 06 08 09 0A 0C 0D 0E 40 41 42 50 51 52 44 45 46 54 55 56 90 91 92 94 95 96 C0 C1 C2 OUTPUT VI_1 VI_2 VI_3 VI_4 VI_5 VI_6 VI_7 VI_8 VI_9 VI_10 VI_11 VI_12 VI_1(Y) VI_2(Y) VI_3(Y) VI_1(Y) VI_2(Y) VI_3(Y) VI_4(Y) VI_5(Y) VI_6(Y) VI_4(Y) VI_5(Y) VI_6(Y) VI_1(Y) VI_2(Y) VI_3(Y) VI_4(Y) VI_5(Y) VI_6(Y) VI_1(CVBS) VI_2(CVBS) VI_3(CVBS) Copyright © 2005­2010, Texas Instruments Incorporated Internal Control Registers Submit Documentation Feedback Product Folder Link(s): TVP5160 43 TVP5160 SLES135C ­ FEBRUARY 2005 ­ REVISED MAY 2010 www. ti. com Table 3-5. AFE Gain Control Subaddress Default 7 01h 0Fh 6 Reserved Bit 3: Bit 2: Bit 1: AGC: 1b must be written to this bit 1b must be written to this bit 1b must be written to this bit Controls automatic gain 0 = Manual 1 = Enable auto gain (default) 5 4 3 1 2 1 1 1 0 AGC This setting only affects the analog front-end (AFE). The brightness and contrast controls are not affected by these settings. Table 3-6. Video Standard Select Subaddress Default 7 01h 00h 6 Reserved Video standard [3:0]: CVBS and S-Video 0000 = Autoswitch mode (default) 0001 = (M, J) NTSC 0010 = (B, D, G, H, I, N) PAL 0011 = (M) PAL 0100 = (Combination-N) PAL 0101 = NTSC 4. 43 0110 = SECAM 0111 = PAL 60 1000 = Reserved 1001 = Reserved 1010 = Reserved Component video Autoswitch mode (default) Interlaced 525 (480i) Interlaced 625 (576i) Reserved Reserved Reserved Reserved Reserved Reserved NTSC Progressive 525 (480p) PAL Progressive 625 (576p) 5 4 3 2 1 Video standard [3:0] 0 The user can force the device to operate in a particular video standard mode by writing the appropriate value into this register. Changing these bits will cause some register settings to be reset to their defaults. Table 3-7. Operation Mode Subaddress Default 7 01h 00h 6 5 4 Reserved 3 2 1 0 Power save Power save 0 Normal operation (default) = 1 Power save mode. Reduces the clock speed of the internal processor and switches off the ADCs. I2C interface is active and all = current operating settings are preserved. 44 Internal Control Registers Submit Documentation Feedback Product Folder Link(s): TVP5160 Copyright © 2005­2010, Texas Instruments Incorporated TVP5160 www. ti. com SLES135C ­ FEBRUARY 2005 ­ REVISED MAY 2010 Table 3-8. Autoswitch Mask Subaddress Default 7 Reserved 04h 23h 6 PAL 60 5 SECAM 4 NTSC 4. 43 3 (Nc) PAL 2 (M) PAL 1 PAL 0 (M, J) NTSC Autoswitch mode mask: Limits the video formats between which autoswitch is possible. [. . . ] In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. [. . . ]