User manual TEXAS INSTRUMENTS TVP5154A DATASHEET 09-2010

[. . . ] TVP5154A www. ti. com SLES214C ­ DECEMBER 2007 ­ REVISED SEPTEMBER 2010 4-Channel Low-Power PAL/NTSC/SECAM Video Decoder With Independent Scalers and Fast Lock Check for Samples: TVP5154A 1 Introduction 1. 1 1 Features · Internal Phase-Locked Loop (PLL) for Line-Locked Clock (Separate for Each Channel) and Sampling · Sub-Carrier Genlock Output for Synchronizing Color Sub-Carrier of External Encoder · Standard Programmable Video Output Format ­ ITU-R BT. 656, 8-Bit 4:2:2 With Embedded Syncs ­ 8-Bit 4:2:2 With Discrete Syncs · Advanced Programmable Video Output Formats ­ 2× Over-Sampled Raw Vertical Blanking Interval (VBI) Data During Active Video ­ Sliced VBI Data During Horizontal Blanking or Active Video · VBI Modes Supported: ­ Teletext (NABTS, WST) ­ Closed-Caption Decode With FIFO, and Extended Data Services (EDS) ­ Wide Screen Signaling (WSS), Video Program System (VPS), Copy Generation Management System (CGMS), Vertical Interval Time Code (VITC) ­ Gemstar 1×/2× Electronic Program Guide Compatible Mode ­ Custom Configuration Mode Allows User to Program the Slice Engine for Unique VBI Data Signals · Improved Fast Lock Mode Can Be Used When Input Video Standard Is Known and Signals on Switching Channels Are Clean · Four Possible I2C Addresses Allowing 16 Decoder Channels on a Single I2C Bus · Available in Commercial (0°C to 70°C) and Industrial (­40°C to 85°C) Temperature Ranges · Four Separate Video Decoder Channels With Features for Each Channel: ­ Accept NTSC (J, M, 4. 43), PAL (B, D, G, H, I, M, N, Nc), and SECAM (B, D, G, K, K1, L) Video ­ Support ITU-R BT. 601 Standard Sampling ­ High-Speed 9-Bit Analog-to-Digital Converter (ADC) ­ Two Composite Inputs or One S-Video Input (for Each Channel) ­ Fully Differential CMOS Analog Preprocessing Channels With Clamping and Automatic Gain Control (AGC) for Best Signal to Noise (SNR) Performance ­ Brightness, Contrast, Saturation, Hue, and Sharpness Control Through Inter-Integrated Circuit (I2C) ­ Complementary 4-Line (3-H Delay) Adaptive Comb Filters for Both Cross-Luminance and Cross-Chrominance Noise Reduction ­ Patented Architecture for Locking to Weak, Noisy, or Unstable Signals · Four Independent Polymorphic Scalers · Single or Concurrent Scaled and Unscaled Outputs Via Dual Clocking Data, Interleaved 54-MHz Data or Single 27-MHz Clock · Scaled/Unscaled Image Toggle Mode Gives Variable Field Rate for Both Scaled and Unscaled Video · Low Power Consumption: 700 mW Typical · 128-Pin Thin Quad Flat Pack (TQFP) Package · Single 14. 31818-MHz Crystal for All Standards and All Channels 1. 2 Description The TVP5154A device is a 4-channel, low-power, NTSC/PAL/SECAM video decoder. Available in a space-saving 128-pin thin quad flat pack (TQFP) package, each channel of the TVP5154A decoder converts NTSC, PAL, or SECAM video signals to 8-bit ITU-R BT. 656 format. Discrete syncs are also 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. [. . . ] 1111 1111 = 255 (maximum) 1000 0000 = 128 (default) 0000 0000 = 0 (no color) The total chrominance gain relative to the nominal chrominance gain as a function of the Saturation [7:0] setting is as follows. Chrominance Gain = nominal_chrominance_gain × (Saturation[7:0] / 128) 7. 2. 12 Hue Control Register (does not apply to SECAM) Address Default 7 0Bh 00h 6 5 4 Hue control Hue control: 0111 1111 = +180 degrees 0000 0000 = 0 degrees (default) 1000 0000 = ­180 degrees 3 2 1 0 Copyright © 2007­2010, Texas Instruments Incorporated Internal Control Registers Submit Documentation Feedback Product Folder Link(s): TVP5154A 35 TVP5154A SLES214C ­ DECEMBER 2007 ­ REVISED SEPTEMBER 2010 www. ti. com 7. 2. 13 Contrast Control Register Address Default 7 0Ch 80h 6 5 4 Contrast [7:0] Contrast [7:0]: This register works for CVBS and S-Video luminance. 1111 1111 to 1101 Reserved 0000 = 1100 1111 = 207 (maximum contrast) 1000 0000 = 128 (default) 0000 0000 = 0 (minimum contrast) The total luminance gain relative to the nominal luminance gain as a function of the Contrast [7:0] setting is as follows. Luminance Gain = nominal_luminance_gain × (Contrast[7:0] / 128) Note: Luminance peak processing (see bit 1 of subaddress: 02h) may limit the upper end of the contrast control range. Note: Whenever the contrast control setting is modified, the brightness control setting must be modified immediately afterward to maintain the proper output black level. 3 2 1 0 7. 2. 14 Address Default Outputs and Data Rates Select Register 0Dh 47h 6 YCbCr output code range 5 CbCr code format 4 3 YCbCr data path bypass 2 1 0 YCbCr output format 7 Reserved YCbCr output code range: 0 = ITU-R BT. 601 coding range (Y ranges from 16 to 235. U and V range from 16 to 240) 1 = Extended coding range (Y, U, and V range from 1 to 254) (default) CbCr code format: 0 = Offset binary code (2s complement + 128) (default) 1 = Straight binary code (2s complement) YCbCr data path bypass: 00 = Normal operation (default) 01 = Decimation filter output connects directly to the YCbCr output pins. This data is similar to the digitized composite data, but the HBLANK area is replaced with ITU-R BT. 656 digital blanking. 11 = Reserved YCbCr output format: 000 = 8-bit 4:2:2 YCbCr with discrete sync output 001 = Reserved 010 = Reserved 011 = Reserved 100 = Reserved 101 = Reserved 110 = Reserved 111 = 8-bit ITU-R BT. 656 interface with embedded sync output (default) 36 Internal Control Registers Submit Documentation Feedback Product Folder Link(s): TVP5154A Copyright © 2007­2010, Texas Instruments Incorporated TVP5154A www. ti. com SLES214C ­ DECEMBER 2007 ­ REVISED SEPTEMBER 2010 7. 2. 15 Luminance Processing Control #3 Register Address Default 7 0Eh 00h 6 5 Reserved Luminance filter stop band bandwidth (MHz): 00 = No notch (default) 01 = Notch 1 10 = Notch 2 11 = Notch 4 3 2 1 0 Luminance trap filter select Luminance filter select [1:0] selects one of the four chroma trap (notch) filters to produce luminance signal by removing the chrominance signal from the composite video signal. The stopband of the chroma trap filter is centered at the chroma subcarrier frequency, with stopband bandwidth controlled by the two control bits. Luma Filter Selection WCF FILTER SELECT 00 0 01 10 11 00 1 01 10 11 NTSC/PAL/SECAM ITU-R BT. 601 1. 2214 0. 8782 0. 7297 0. 4986 1. 4170 1. 0303 0. 8438 0. 5537 Copyright © 2007­2010, Texas Instruments Incorporated Internal Control Registers Submit Documentation Feedback Product Folder Link(s): TVP5154A 37 TVP5154A SLES214C ­ DECEMBER 2007 ­ REVISED SEPTEMBER 2010 www. ti. com 7. 2. 16 Address Default 7 Reserved Configuration Shared Pins Register 0Fh 08h 6 FID PIN 5 Reserved 4 PALI PIN 3 FID/GLCO 2 VSYNC/PALI 1 INTREQ/GPCL/VBLK 0 CLK/PCLK FID PIN function select: 0 = FID (default, if bit 3 is selected to output FID) 1 = Lock indicator (indicates whether the device is locked vertically) PALI PIN function select: 0 = PALI (default, if bit 2 is selected to output PALI) 1 = Lock indicator (indicates whether the device is locked horizontally) FID/GLCO function select (see register 03h, Section 7. 2. 4, for enhanced functionality): 0 = FID 1 = GLCO (default) VSYNC/PALI function select (see register 03h, Section 7. 2. 4, for enhanced functionality): 0 = VSYNC (default) 1 = PALI INTREQ/GPCL/VBLK function select: 0 = INTREQ (default) 1 = GPCL or VBLK depending on bit 7 of register 03h CLK/PCLK (pins 42, 61, 84, 103) function select: 0 = CLK at 27 MHz (default) 1 = PCLK (1× pixel clock frequency at 13. 5 MHz) See Figure 7-1 for the relationship between the configuration shared pins. 7. 2. 17 Address Default 7 Active Video Cropping Start Pixel MSB for Unscaled Data Register 11h 00h 6 5 4 3 AVID start pixel MSB [9:2] 2 1 0 Active video cropping start pixel MSB [9:2], set this register first before setting register 12h. The TVP5154A decoder updates the AVID start values only when register 12h is written to. This start pixel value is relative to the default values of the AVID start pixel. 38 Internal Control Registers Submit Documentation Feedback Product Folder Link(s): TVP5154A Copyright © 2007­2010, Texas Instruments Incorporated TVP5154A www. ti. com SLES214C ­ DECEMBER 2007 ­ REVISED SEPTEMBER 2010 7. 2. 18 Address Default 7 Active Video Cropping Start Pixel LSB for Unscaled Data Register 12h 00h 6 5 Reserved 4 3 2 AVID active 1 0 AVID start pixel LSB [1:0] AVID active: 0 = AVID out active in VBLK (default) 1 = AVID out inactive in VBLK AVID start [9:0] (combined registers 11h and 12h): 01 1111 1111 = 511 00 0000 0001 = 1 00 0000 0000 = 0 (default) 11 1111 1111 = ­1 10 0000 0000 = ­512 Active video cropping start pixel LSB [1:0]: The TVP5154A decoder updates the AVID start values only when this register is written to. 7. 2. 19 Address Default 7 Active Video Cropping Stop Pixel MSB LSB for Unscaled Data Register 13h 00h 6 5 4 3 AVID stop pixel MSB [9:2] 2 1 0 Active video cropping stop pixel MSB [9:2], set this register first before setting the register 14h. The TVP5154A decoder updates the AVID stop values only when register 14h is written to. This stop pixel value is relative to the default values of the AVID stop pixel. 7. 2. 20 Address Default 7 Active Video Cropping Stop Pixel LSB for Unscaled Data Register 14h 00h 6 5 Reserved 4 3 2 1 0 AVID stop pixel LSB [1:0] Active video cropping stop pixel LSB [1:0]: The number of pixels of active video must be an even number. The TVP5154A decoder updates the AVID stop values only when this register is written to. AVID stop [9:0] (combined registers 13h and 14h): 01 1111 1111 = 511 00 0000 0001 = 1 00 0000 0000 = 0 (default) (see Figure 3-5) and Figure 3-6) 11 1111 1111 = ­1 10 0000 0000 = ­512 Copyright © 2007­2010, Texas Instruments Incorporated Internal Control Registers Submit Documentation Feedback Product Folder Link(s): TVP5154A 39 TVP5154A SLES214C ­ DECEMBER 2007 ­ REVISED SEPTEMBER 2010 www. ti. com 7. 2. 21 Address Default Genlock and RTC Register 15h 01h 6 Reserved 5 F/V bit control 4 3 Auto inc 2 1 GLCO/RTC 0 7 Stable syncs Stable syncs 0 = Output F and V bits follow the input signal producing fixed vertical blanking periods by adapting the active video. 1 = Output F and V bits produce fixed active video periods by adapting the vertical blanking. F/V Bit Control BIT 5 0 BIT 4 0 NUMBER OF LINES Standard Nonstandard even Nonstandard odd 0 1 1 1 0 1 Standard Nonstandard Standard Nonstandard Illegal F BIT ITU-R BT. 656 Force to 1 Toggles ITU-R BT. 656 Toggles ITU-R BT. 656 Pulse mode V BIT ITU-R BT. 656 Switch at field boundary Switch at field boundary ITU-R BT. 656 Switch at field boundary ITU-R BT. 656 Switch at field boundary Auto inc: When this bit is set to 1, subsequent reading/writing from/to back door registers automatically increment the address index. GLCO/RTC Control BIT 2 0 0 1 1 BIT 1 x x x x BIT 0 0 1 0 1 GLCO RTC output mode 0 (default) GLCO RTC output mode 1 GENLOCK/RTC MODE All other values are reserved. Figure 6-1 shows the timing of GLCO and the timing of RTC. 40 Internal Control Registers Submit Documentation Feedback Product Folder Link(s): TVP5154A Copyright © 2007­2010, Texas Instruments Incorporated TVP5154A www. ti. com SLES214C ­ DECEMBER 2007 ­ REVISED SEPTEMBER 2010 7. 2. 22 Address Default 7 Horizontal Sync (HSYNC) Start Register 16h 80h 6 5 4 HSYNC start 3 2 1 0 HSYNC start: 1111 1111 = 1111 1110 = 1000 0001 = 1000 0000 = 0111 1111 = 0111 1110 = 0000 0000 = ­127 × 4 pixel clocks ­126 × 4 pixel clocks ­1 × 4 pixel clocks 0 pixel clocks (default) 1 × 4 pixel clocks 2 × 4 pixel clocks 128 × 4 pixel clocks BT. 656 EAV Code BT. 656 SAV Code YOUT[7:0] U Y V Y F F 0 0 0 0 X Y 8 0 1 0 8 0 1 0 F F 0 0 0 0 X Y U Y HSYNC AVID 128 SCLK Nhbhs Nhb Start of Digital Active Line Figure 7-2. Clock Delays (CLKs) STANDARD NTSC PAL SECAM Nhbhs 16 20 40 Nhb 272 284 280 Detailed timing information is also available in Section 3. 12, Synchronization Signals. Copyright © 2007­2010, Texas Instruments Incorporated Internal Control Registers Submit Documentation Feedback Product Folder Link(s): TVP5154A 41 TVP5154A SLES214C ­ DECEMBER 2007 ­ REVISED SEPTEMBER 2010 www. ti. com 7. 2. 23 Address Default Ancillary SAV/EAV Control 17h 52h 6 Scaler PD 5 Include scale ancillary 4 Include scale SAV 3 Include scale EAV 2 Include unscale ancillary 1 Include unscale SAV 0 Include unscale EAV 7 Reserved Include unscaled EAV: 0 = AVID period does not include the EAV sync codes (default). Include unscaled SAV: 0 = AVID period does not include the SAV sync codes. [. . . ] In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. [. . . ]