User manual TEXAS INSTRUMENTS TMS320VC5401 DATA MANUAL REV D

[. . . ] TMS320VC5401 Fixed-Point Digital Signal Processor Data Manual Literature Number: SPRS153D December 2000 - Revised October 2008 PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Revision History REVISION HISTORY This data sheet revision history highlights the technical changes made to the SPRS153C device-specific data sheet to make it an SPRS153D revision. Scope: This document has been reviewed for technical accuracy; the technical content is up-to-date as of the specified release date with the following changes. PAGE(S) NO. [. . . ] To accommodate applications that require an external reference clock for the sample rate generator, the 5401 McBSPs allow either the receive clock pin (BCLKR) or the transmit clock pin (BCLKX) to be configured as the input clock to the sample rate generator. This enhancement is enabled through two register bits: pin control register (PCR) bit 7 - enhanced sample clock mode (SCLKME), and sample rate generator register 2 (SRGR2) bit 13 - McBSP sample rate generator clock mode (CLKSM). SCLKME is an addition to the PCR contained in the McBSPs on previous C5000 DSP devices. For a description of the remaining bits, see TMS320C54x DSP Reference Set, Volume 5: Enhanced Peripherals (literature number SPRU302). 15 Reserved R, +0 7 SCLKME RW, +0 6 CLKS_STAT R, +0 14 13 XIOEN RW, +0 5 DX_STAT R, +0 12 RIOEN RW, +0 4 DR_STAT R, +0 11 FSXM RW, +0 3 FSXP RW, +0 10 FSRM RW, +0 2 FSRP RW, +0 9 CLKXM RW, +0 1 CLKXP RW, +0 8 CLKRM RW, +0 0 CLKRP RW, +0 LEGEND: R = Read, W = Write, n = value present after reset Figure 3-9. Pin Control Register (PCR) C5000 is a trademark of Texas Instruments. December 2000 - Revised October 2008 SPRS153D 31 Functional Overview The selection of the sample rate generator (SRG) clock input source is made by the combination of the CLKSM and SCLKME bit values as shown in Table 3-6. Sample Rate Generator Clock Source Selection SCLKME 0 0 1 1 CLKSM 0 1 0 1 SRG Clock Source CLKS (not available as a pin on 5401) CPU clock BCLKR pin BCLKX pin When either of the bidirectional pins, BCLKR or BCLKX, is configured as the clock input, its output buffer is automatically disabled. For example, with SCLKME = 1 and CLKSM = 0, the BCLKR pin is configured as the SRG input. In this case, both the transmitter and receiver circuits can be synchronized to the SRG output by setting the PCR bits (9:8) for CLKXM = 1 and CLKRM = 1. However, the SRG output is only driven onto the BCLKX pin because the BCLKR output is automatically disabled. The McBSP supports independent selection of multiple channels for the transmitter and receiver. When multiple channels are selected, each frame represents a time-division multiplexed (TDM) data stream. In using time-division multiplexed data streams, the CPU may only need to process a few of them. Thus, to save memory and bus bandwidth, multichannel selection allows independent enabling of particular channels for transmission and reception. Up to a maximum of 128 channels in a bit stream can be enabled or disabled. 3. 6 Hardware Timer The 5401 device features one 16-bit timing circuit with a 4-bit prescaler. The main counter of each timer is decremented by one every CPU clock cycle. Each time the counter decrements to 0, a timer interrupt is generated. The timer can be stopped, restarted, reset, or disabled by specific control bits. 3. 7 Clock Generator The clock generator provides clocks to the 5401 device, and consists of an internal oscillator and a phase-locked loop (PLL) circuit. The clock generator requires a reference clock input, which can be provided by using a crystal resonator with the internal oscillator, or from an external clock source. NOTE: All revisions of the 5401 can be operated with an external clock source, provided that the proper voltage levels be driven on the X2/CLKIN pin. It should be noted that the X2/CLKIN pin is referenced to the device 1. 8 V power supply (CVDD), rather than the 3 V I/O supply (DVDD). Refer to the recommended operating conditions section of this document for the allowable voltage levels of the X2/CLKIN pin. The reference clock input is then divided by two (DIV mode) to generate clocks for the 5401 device, or the PLL circuit can be used (PLL mode) to generate the device clock by multiplying the reference clock frequency by a scale factor, allowing use of a clock source with a lower frequency than that of the CPU. The PLL is an adaptive circuit that, once synchronized, locks onto and tracks an input clock signal. When the PLL is initially started, it enters a transitional mode during which the PLL acquires lock with the input signal. [. . . ] MicroStar BGAt configuration MicroStar BGA is a trademark of Texas Instruments Incorporated. POST OFFICE BOX 655303 · DALLAS, TEXAS 75265 0, 80 1 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. [. . . ]