User manual TEXAS INSTRUMENTS TMS320DM6467T DATA MANUAL REV B

[. . . ] TMS320DM6467T www. ti. com SPRS605B ­ JULY 2009 ­ REVISED JULY 2010 TMS320DM6467T Digital Media System-on-Chip Check for Samples: TMS320DM6467T 1 Digital Media System-on-Chip (DMSoC) 1. 1 1 Features ­ 128K-Byte L2 Unified Mapped RAM/Cache (Flexible RAM/Cache Allocation) ARM926EJ-S Core ­ Support for 32-Bit and 16-Bit (Thumb® Mode) Instruction Sets ­ DSP Instruction Extensions and Single Cycle MAC ­ ARM® Jazelle® Technology ­ EmbeddedICE-RTTM Logic for Real-Time Debug ARM9 Memory Architecture ­ 16K-Byte Instruction Cache ­ 8K-Byte Data Cache ­ 32K-Byte RAM ­ 8K-Byte ROM Embedded Trace BufferTM (ETB11TM) With 4KB Memory for ARM9 Debug Endianness: Little Endian for ARM and DSP Dual Programmable High-Definition Video Image Co-Processor (HDVICP) Engines ­ Supports a Range of Encode, Decode, and Transcode Operations · H. 264, MPEG2, VC1, MPEG4 SP/ASP 150-MHz Video Port Interface (VPIF) ­ Two 8-Bit SD (BT. 656), Single 16-Bit HD (BT. 1120), or Single Raw (8-/10-/12-Bit) Video Capture Channels ­ Two 8-Bit SD (BT. 656) or Single 16-Bit HD (BT. 1120) Video Display Channels Video Data Conversion Engine (VDCE) ­ Horizontal and Vertical Downscaling ­ Chroma Conversion (4:2:24:2:0) Two Transport Stream Interface (TSIF) Modules (One Parallel/Serial and One Serial Only) ­ TSIF for MPEG Transport Stream ­ Simultaneous Synchronous or Asynchronous Input/Output Streams ­ Absolute Time Stamp Detection ­ PID Filter With 7 PID Filter Tables ­ Corresponding Clock Reference Generator (CRGEN) Modules for System Time-Clock Recovery · High-Performance Digital Media SoC ­ 1-GHz C64x+TM Clock Rate ­ 500-MHz ARM926EJ-STM Clock Rate ­ Eight 32-Bit C64x+ Instructions/Cycle ­ 8000 C64x+ MIPS ­ Fully Software-Compatible With C64x / ARM9TM ­ Industrial Temperature Devices Available · Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x+TM DSP Core ­ Eight Highly Independent Functional Units · Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle · Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle ­ Load-Store Architecture With Non-Aligned Support ­ 64 32-Bit General-Purpose Registers ­ Instruction Packing Reduces Code Size ­ All Instructions Conditional ­ Additional C64x+TM Enhancements · Protected Mode Operation · Exceptions Support for Error Detection and Program Redirection · Hardware Support for Modulo Loop Operation · C64x+ Instruction Set Features ­ Byte-Addressable (8-/16-/32-/64-Bit Data) ­ 8-Bit Overflow Protection ­ Bit-Field Extract, Set, Clear ­ Normalization, Saturation, Bit-Counting ­ Compact 16-Bit Instructions ­ Additional Instructions to Support Complex Multiplies · C64x+ L1/L2 Memory Architecture ­ 32K-Byte L1P Program RAM/Cache (Direct Mapped) ­ 32K-Byte L1D Data RAM/Cache (2-Way Set-Associative) 1 · · · · · · · · Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2009­2010, Texas Instruments Incorporated TMS320DM6467T SPRS605B ­ JULY 2009 ­ REVISED JULY 2010 www. ti. com · External Memory Interfaces (EMIFs) ­ Up to 400-MHz 32-Bit DDR2 SDRAM Memory Controller With 512M-Byte Address Space (1. 8-V I/O) ­ Asynchronous16-Bit Wide EMIF (EMIFA) With 128M-Byte Address Reach · Flash Memory Interfaces ­ NOR (8-/16-Bit-Wide Data) ­ NAND (8-/16-Bit-Wide Data) · Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels) ­ Programmable Default Burst Size · 10/100/1000 Mb/s Ethernet MAC (EMAC) ­ IEEE 802. 3 Compliant (3. 3-V I/O Only) ­ Supports MII and GMII Media Independent Interfaces ­ Management Data I/O (MDIO) Module · USB Port With Integrated 2. 0 PHY ­ USB 2. 0 High-/Full-Speed Client ­ USB 2. 0 High-/Full-/Low-Speed Host (Mini-Host, Supporting One External Device) · 32-Bit, 66-MHz, 3. 3 V Peripheral Component Interconnect (PCI) Master/Slave Interface ­ Conforms to PCI Specification 2. 3 · Two 64-Bit General-Purpose Timers (Each Configurable as Two 32-Bit Timers) · One 64-Bit Watch Dog Timer · Three Configurable UART/IrDA/CIR Modules (One With Modem Control Signals) ­ Supports up to 1. 8432 Mbps UART ­ SIR and MIR (0. 576 MBAUD) ­ CIR With Programmable Data Encoding · One Serial Peripheral Interface (SPI) With Two Chip-Selects · Master/Slave Inter-Integrated Circuit (I2C BusTM) · Two Multichannel Audio Serial Ports (McASPs) ­ One Four Serializer Transmit/Receive Port ­ One Single DIT Transmit Port for S/PDIF · 32-Bit Host Port Interface (HPI) · VLYNQTM Interface (FPGA Interface) · Two Pulse Width Modulator (PWM) Outputs · ATA/ATAPI I/F (ATA/ATAPI-6 Specification) · Up to 33 General-Purpose I/O (GPIO) Pins (Multiplexed With Other Device Functions) · On-Chip ARM ROM Bootloader (RBL) · Individual Power-Saving Modes for ARM/DSP · Flexible PLL Clock Generators · IEEE-1149. 1 (JTAG) BoundaryScan-Compatible · 529-Pin Pb-Free BGA Package (ZUT Suffix), 0. 8-mm Ball Pitch · 0. 09-mm/7-Level Cu Metal Process (CMOS) · 3. 3-V and 1. 8-V I/O, 1. 3-V Internal · Applications: ­ Video Encode/Decode/Transcode/Transrate ­ Digital Media ­ Networked Media Encode/Decode ­ Video Imaging ­ Video Infrastructure ­ Video Conferencing · Community Resources ­ TI E2E Community ­ TI Embedded Processors Wiki 2 Digital Media System-on-Chip (DMSoC) Copyright © 2009­2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6467T TMS320DM6467T www. ti. com SPRS605B ­ JULY 2009 ­ REVISED JULY 2010 1. 2 Description The TMS320DM6467T (also referenced as DM6467T) leverages TI's DaVinciTM technology to meet the networked media encode and decode application processing needs of next-generation embedded devices. The DM6467T enables OEMs and ODMs to quickly bring to market devices featuring robust operating systems support, rich user interfaces, high processing performance, and long battery life through the maximum flexibility of a fully integrated mixed processor solution. [. . . ] Oscillator ground (DEV_VSS and AUX_VSS) must be kept separate from other grounds and connected directly to the crystal load capacitor ground. DDR_VREF is expected to equal 0. 5DVDDR2 of the transmitting device and to track variations in the DVDDR2. Copyright © 2009­2010, Texas Instruments Incorporated Device Operating Conditions 137 Submit Documentation Feedback Product Folder Link(s): TMS320DM6467T TMS320DM6467T SPRS605B ­ JULY 2009 ­ REVISED JULY 2010 www. ti. com 6. 3 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Temperature (Unless Otherwise Noted) PARAMETER Low/full speed: USB_DN and USB_DP High speed: USB_DN and USB_DP TEST CONDITIONS (1) MIN 2. 8 360 TYP MAX USB_VDDA3P3 440 UNIT V mV V V VOH High-level output voltage (3. 3V I/O except PCI-capable and I2C pins) High-level output voltage (3. 3V I/O PCI-capable pins) Low/full speed: USB_DN and USB_DP High speed: USB_DN and USB_DP DVDD33 = MIN, IOH = MAX IOH = ­0. 5 mA, DVDD33 = 3. 3 V 2. 4 0. 9DVDD33 (2) 0. 0 ­10 DVDD33 = MIN, IOL = MAX IOL = 1. 5 mA, DVDD33 = 3. 3 V IO = 3 mA VI = VSS to DVDD33 without opposing internal resistor 0 1. 14 1. 2 0. 3 10 0. 4 0. 1DVDD33 (2) V mV V V V V mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA VOL Low-level output voltage (3. 3V I/O except PCI-capable and I2C pins) Low-level output voltage (3. 3V I/O PCI-capable pins) Low-level output voltage (3. 3V I/O I2C pins) 0. 4 1. 26 ±20 VLDO USB_VDDA1P2LDO output voltage Input current [DC] (except I2C and PCI-capable pins) VI = VSS to DVDD33 with opposing internal pullup resistor (4) VI = VSS to DVDD33 with opposing internal pulldown resistor (4) 50 ­250 100 ­100 250 ­50 ±20 ±50 II (3) Input current [DC] (I2C) VI = VSS to DVDD33 0 < VI < DVDD33 = 3. 3 V without opposing internal resistor Input current (PCI-capable pins) [DC] (5) 0 < VI < DVDD33 = 3. 3 V with opposing internal pullup resistor (4) 0 < VI < DVDD33 = 3. 3 V with opposing internal pulldown resistor (4) GMTCLK, MTXD[7:0], MTXEN DDR2; VOH = DVDDR2 ­ 0. 4 V 50 ­250 250 ­50 ­8 ­8 ­0. 5 (2) IOH High-level output current [DC] PCI-capable pins (PCI pin function only) All other peripherals GMTCLK, MTXD[7:0], MTXEN DDR2; VOL = 0. 4 V ­4 8 8 1. 5 (2) IOL Low-level output current [DC] PCI-capable pins (PCI pin function only) All other peripherals VO = DVDD33 or VSS; internal pull disabled VO = DVDD33 or VSS; internal pull enabled CVDD = 1. 3 V, DSP clock = 1 GHz ARM Clock = 500 MHz, DDR Clock = 400 MHz DVDD = 3. 3 V, DSP clock = 1 GHz ARM Clock = 500 MHz, DDR Clock = 400 MHz ±100 4 ±20 IOZ (6) I/O Off-state output current ICDD Core (CVDD, DEV_CVDD, AUX_CVDD) supply current (7) 3. 3V I/O (DVDD33, USB_VDDA3P3) supply current (7) 1792. 22 mA IDDD 25. 66 mA (1) (2) (3) (4) (5) (6) (7) For test conditions shown as MIN, MAX, or TYP, use the appropriate value specified in the recommended operating conditions table. These rated numbers are from the PCI Local Bus Specification Revision 2. 3. The DC specifications and AC specifications are defined in Table 4-3 (DC Specifications for 3. 3V Signaling) and Table 4-4 (AC Specifications for 3. 3V Signaling), respectively. For bi-directional pins, II indicates the input leakage current and off-state (Hi-Z) output leakage current. Applies only to pins with an internal pullup (IPU) or pulldown (IPD) resistor. PCI input leakage currents include Hi-Z output leakage for all bidirectional buffers with 3-state outputs. IOZ applies to output-only pins, indicating off-state (Hi-Z) output leakage current. Measured under the following conditions: 60% DSP CPU utilization; ARM doing typical activity (peripheral configurations, other housekeeping activities); DDR2 Memory Controller at 50% utilization, 50% writes, 32 bits, 50% bit switching at room temperature (25 °C). The actual current draw varies across manufacturing processes and is highly application-dependent. For more details on core and I/O activity, as well as information relevant to board power supply design, see the TMS320DM6467T Power Consumption Summary Application Report (literature number SPRAB64). Device Operating Conditions Copyright © 2009­2010, Texas Instruments Incorporated 138 Submit Documentation Feedback Product Folder Link(s): TMS320DM6467T TMS320DM6467T www. ti. com SPRS605B ­ JULY 2009 ­ REVISED JULY 2010 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Temperature (Unless Otherwise Noted) (continued) PARAMETER IDDD CI Co 1. 8V I/O (DVDDR2, PLL1VPRW18, PLL2VPRW18, DEV_DVDD18, AUX_DVDD18, USB_VDD1P8) supply current (7) Input capacitance Output capacitance TEST CONDITIONS (1) MIN TYP 214. 02 MAX UNIT mA DVDD = 1. 8 V, DSP clock = 1 GHz ARM Clock = 500 MHz, DDR Clock = 400 MHz 4 4 pF pF Copyright © 2009­2010, Texas Instruments Incorporated Device Operating Conditions 139 Submit Documentation Feedback Product Folder Link(s): TMS320DM6467T TMS320DM6467T SPRS605B ­ JULY 2009 ­ REVISED JULY 2010 www. ti. com 7 Peripheral Information and Electrical Specifications 7. 1 Parameter Information Tester Pin Electronics Data Sheet Timing Reference Point 42 3. 5 nH Transmission Line Z0 = 50 (see Note) Output Under Test Device Pin (see Note) 4. 0 pF 1. 85 pF NOTE: The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects must be taken into account. A transmission line with a delay of 2 ns can be used to produce the desired transmission line effect. It is not necessary to add or subtract the transmission line delay (2 ns) from the data sheet timings. Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin. Figure 7-1. Test Load Circuit for AC Timing Measurements The load capacitance value stated is only for characterization and measurement of AC timing signals. This load capacitance value does not indicate the maximum load the device is capable of driving. 7. 1. 1 1. . 8-V and 3. 3-V Signal Transition Levels All input and output timing parameters are referenced to Vref for both "0" and "1" logic levels. Input and Output Voltage Reference Levels for AC Timing Measurements All rise and fall transition timing parameters are referenced to VIL MAX and VIH MIN for input clocks, VOL MAX and VOH MIN for output clocks. Vref = VIH MIN (or VOH MIN) Vref = VIL MAX (or VOL MAX) Figure 7-3. Rise and Fall Transition Time Voltage Reference Levels 7. 1. 2 3. 3-V Signal Transition Rates All timings are tested with an input edge rate of 4 volts per nanosecond (4 V/ns). 7. 1. 3 Timing Parameters and Board Routing Analysis The timing parameter values specified in this data manual do not include delays by board routings. As a good board design practice, such delays must always be taken into account. Timing values may be 140 Peripheral Information and Electrical Specifications Copyright © 2009­2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6467T TMS320DM6467T www. ti. com SPRS605B ­ JULY 2009 ­ REVISED JULY 2010 adjusted by increasing/decreasing such delays. [. . . ] In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. [. . . ]