User manual TEXAS INSTRUMENTS TMS320DM6467 FEATURES 10-2010

[. . . ] TMS320DM6467 www. ti. com SPRS403G ­ DECEMBER 2007 ­ REVISED OCTOBER 2010 TMS320DM6467 Digital Media System-on-Chip Check for Samples: TMS320DM6467 1 Digital Media System-on-Chip (DMSoC) 1. 1 12 Features · C64x+ L1/L2 Memory Architecture ­ 32K-Byte L1P Program RAM/Cache (Direct Mapped) ­ 32K-Byte L1D Data RAM/Cache (2-Way Set-Associative) ­ 128K-Byte L2 Unified Mapped RAM/Cache (Flexible RAM/Cache Allocation) · ARM926EJ-S Core ­ Support for 32-Bit and 16-Bit (Thumb® Mode) Instruction Sets ­ DSP Instruction Extensions and Single Cycle MAC ­ ARM® Jazelle® Technology ­ EmbeddedICE-RTTM Logic for Real-Time Debug · ARM9 Memory Architecture ­ 16K-Byte Instruction Cache ­ 8K-Byte Data Cache ­ 32K-Byte RAM ­ 8K-Byte ROM · Embedded Trace BufferTM (ETB11TM) With 4KB Memory for ARM9 Debug · Endianness: Little Endian for ARM and DSP · Dual Programmable High-Definition Video Image Co-Processor (HDVICP) Engines ­ Supports a Range of Encode, Decode, and Transcode Operations · H. 264, MPEG2, VC1, MPEG4 SP/ASP · 99-/108-MHz Video Port Interface (VPIF) ­ Two 8-Bit SD (BT. 656), Single 16-Bit HD (BT. 1120), or Single Raw (8-/10-/12-Bit) Video Capture Channels ­ Two 8-Bit SD (BT. 656) or Single 16-Bit HD (BT. 1120) Video Display Channels · Video Data Conversion Engine (VDCE) ­ Horizontal and Vertical Downscaling ­ Chroma Conversion (4:2:24:2:0) · Two Transport Stream Interface (TSIF) Modules (One Parallel/Serial and One Serial Only) ­ TSIF for MPEG Transport Stream ­ Simultaneous Synchronous or · High-Performance Digital Media SoC ­ 594-, 729-MHz C64x+TM Clock Rate ­ 297-, 364. 5-MHz ARM926EJ-STM Clock Rate ­ Eight 32-Bit C64x+ Instructions/Cycle ­ 4752, 5832 C64x+ MIPS ­ Fully Software-Compatible With C64x/ARM9TM ­ Supports SmartReflexTM [-594 only] · Class 0 · 1. 05-V and 1. 2-V Adaptive Core Voltage ­ Extended Temp Available [-594 only] ­ Industrial Temp Available [-729 only] · Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x+TM DSP Core ­ Eight Highly Independent Functional Units · Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle · Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle ­ Load-Store Architecture With Non-Aligned Support ­ 64 32-Bit General-Purpose Registers ­ Instruction Packing Reduces Code Size ­ All Instructions Conditional ­ Additional C64x+TM Enhancements · Protected Mode Operation · Exceptions Support for Error Detection and Program Redirection · Hardware Support for Modulo Loop Operation · C64x+ Instruction Set Features ­ Byte-Addressable (8-/16-/32-/64-Bit Data) ­ 8-Bit Overflow Protection ­ Bit-Field Extract, Set, Clear ­ Normalization, Saturation, Bit-Counting ­ Compact 16-Bit Instructions ­ Additional Instructions to Support Complex Multiplies 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. Copyright © 2007­2010, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. TMS320DM6467 SPRS403G ­ DECEMBER 2007 ­ REVISED OCTOBER 2010 www. ti. com · · · · · · · Asynchronous Input/Output Streams ­ Absolute Time Stamp Detection ­ PID Filter With 7 PID Filter Tables ­ Corresponding Clock Reference Generator (CRGEN) Modules for System Time-Clock Recovery External Memory Interfaces (EMIFs) ­ 297-/310. 5-MHz 32-Bit DDR2 SDRAM Memory Controller With 512M-Byte Address Space (1. 8-V I/O) ­ Asynchronous16-Bit-Wide EMIF (EMIFA) With 128M-Byte Address Reach · Flash Memory Interfaces ­ NOR (8-/16-Bit-Wide Data) ­ NAND (8-/16-Bit-Wide Data) Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels) ­ Programmable Default Burst Size 10/100/1000 Mb/s Ethernet MAC (EMAC) ­ IEEE 802. 3 Compliant (3. 3-V I/O Only) ­ Supports MII and GMII Media Independent Interfaces ­ Management Data I/O (MDIO) Module USB Port With Integrated 2. 0 PHY ­ USB 2. 0 High-/Full-Speed Client ­ USB 2. 0 High-/Full-/Low-Speed Host (Mini-Host, Supporting One External Device) 32-Bit, 33-MHz, 3. 3-V Peripheral Component Interconnect (PCI) Master/Slave Interface ­ Conforms to PCI Specification 2. 3 Two 64-Bit General-Purpose Timers (Each Configurable as Two 32-Bit Timers) One 64-Bit Watchdog Timer · Three Configurable UART/IrDA/CIR Modules (One With Modem Control Signals) ­ Supports up to 1. 8432 Mbps UART ­ SIR and MIR (0. 576 MBAUD) ­ CIR With Programmable Data Encoding · One Serial Peripheral Interface (SPI) With Two Chip-Selects · Master/Slave Inter-Integrated Circuit (I2C BusTM) · Two Multichannel Audio Serial Ports (McASPs) ­ One Four-Serializer Transmit/Receive Port ­ One Single DIT Transmit Port for S/PDIF · 32-Bit Host Port Interface (HPI) · VLYNQTM Interface (FPGA Interface) · Two Pulse Width Modulator (PWM) Outputs · ATA/ATAPI I/F (ATA/ATAPI-6 Specification) · Up to 33 General-Purpose I/O (GPIO) Pins (Multiplexed With Other Device Functions) · On-Chip ARM ROM Bootloader (RBL) · Individual Power-Saving Modes for ARM/DSP · Flexible PLL Clock Generators · IEEE-1149. 1 (JTAG) BoundaryScan-Compatible · 529-Pin Pb-Free BGA Package (ZUT Suffix), 0. 8-mm Ball Pitch · 0. 09-mm/7-Level Cu Metal Process (CMOS) · 3. 3-V and 1. 8-V I/O, 1. 2-/1. 05-V Internal · Applications: ­ Video Encode/Decode/Transcode/Transrate ­ Digital Media ­ Networked Media Encode/Decode ­ Video Imaging ­ Video Infrastructure ­ Video Conferencing 2 Digital Media System-on-Chip (DMSoC) Submit Documentation Feedback Product Folder Link(s): TMS320DM6467 Copyright © 2007­2010, Texas Instruments Incorporated TMS320DM6467 www. ti. com SPRS403G ­ DECEMBER 2007 ­ REVISED OCTOBER 2010 1. 2 Description The TMS320DM6467 (also referenced as DM6467) leverages TI's DaVinciTM technology to meet the networked media encode and decode digital media processing needs of next-generation embedded devices. [. . . ] Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Based on JEDEC JESD22-A114E (Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM)). Based on JEDEC JESD22-C101C (Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components). 140 Device Operating Conditions Submit Documentation Feedback Product Folder Link(s): TMS320DM6467 Copyright © 2007­2010, Texas Instruments Incorporated TMS320DM6467 www. ti. com SPRS403G ­ DECEMBER 2007 ­ REVISED OCTOBER 2010 6. 2 Recommended Operating Conditions MIN NORM 1. 14 1. 14 1. 00 3. 14 1. 71 0 0. 49DVDDR2 NOM 1. 2 1. 2 1. 05 3. 3 1. 8 0 0. 5DVDDR2 VSS DVDDR2 2 2. 5 0. 5DVDD33 0. 7DVDD33 0. 65DVDD18 0. 8 0. 3DVDD33 0 0. 3DVDD33 0. 35DVDD18 Default 0 -40 -40 20 20 85 105 85 594 729 MHz MHz °C (A version) (D version) MAX 1. 26 1. 26 1. 1 3. 46 1. 89 0 0. 51DVDDR2 UNIT V V V V V V V V V V V V V V V V V V CVDD Supply voltage, Core (CVDD, DEV_CVDD, AUX_CVDD) (1) SmartReflex [-594V, -594AV only] [see Table 4-39] Supply voltage, I/O, 3. 3V (DVDD33, USB_VDDA3P3) DVDD Supply voltage, I/O, 1. 8V (DVDDR2, PLL1VDD18, PLL2VDD18, DEV_DVDD18, AUX_DVDD18, USB_VDD1P8 (2)) Supply ground (VSS, PLL1VSS, PLL2VSS, DEV_VSS (3) , USB_VSSREF) DDR2 reference voltage (4) DDR2 impedance control, connected via 50- (±5% tolerance) resistor to VSS DDR2 impedance control, connected via 50- (±5% tolerance) resistor to DVDDR2 High-level input voltage, 3. 3 V (except JTAG[TCK], PCI-capable, and I2C pins) High-level input voltage, JTAG [TCK] VIH High-level input voltage, PCI High-level input voltage, I2C High-level input voltage, non-DDR I/O, 1. 8 V Low-level input voltage, 3. 3 V (except PCI-capable and I2C pins) VIL Low-level input voltage, PCI Low-level input voltage, I2C Low-level input voltage, non-DDR I/O, 1. 8 V (3) VSS DDR_VREF DDR_ZP DDR_ZN , AUX_VSS Tc Operating case temperature FSYSCLK1 DSP Operating Frequency (SYSCLK1) -594 -729 (1) (2) (3) (4) Future variants of TI SoC devices may operate at voltages ranging from 0. 9 V to 1. 4 V to provide a range of system power/performance options. TI highly recommends that users design-in a supply that can handle multiple voltages within this range (i. e. , 1. 0 V, 1. 05 V, 1. 1 V, 1. 14 V, 1. 2 V, 1. 26 V with ± 3% tolerances) by implementing simple board changes such as reference resistor values or input pin configuration modifications. Not incorporating a flexible supply may limit the system's ability to easily adapt to future versions of TI SoC devices. Oscillator 1. 8 V power supply (DEV_DVDD18) can be connected to the same 1. 8 V power supply as DVDDR2. Oscillator ground (DEV_VSS and AUX_VSS) must be kept separate from other grounds and connected directly to the crystal load capacitor ground. DDR_VREF is expected to equal 0. 5DVDDR2 of the transmitting device and to track variations in the DVDDR2. Copyright © 2007­2010, Texas Instruments Incorporated Device Operating Conditions Submit Documentation Feedback Product Folder Link(s): TMS320DM6467 141 TMS320DM6467 SPRS403G ­ DECEMBER 2007 ­ REVISED OCTOBER 2010 www. ti. com 6. 3 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Temperature (Unless Otherwise Noted) PARAMETER Low/full speed: USB_DN and USB_DP High speed: USB_DN and USB_DP TEST CONDITIONS (1) MIN 2. 8 360 TYP MAX USB_VDDA3P3 440 UNIT V mV V V VOH High-level output voltage (3. 3V I/O except PCI-capable and I2C pins) High-level output voltage (3. 3V I/O PCI-capable pins) Low/full speed: USB_DN and USB_DP High speed: USB_DN and USB_DP Low-level output voltage (3. 3V I/O except PCI-capable and I2C pins) Low-level output voltage (3. 3V I/O PCI-capable pins) Low-level output voltage (3. 3V I/O I2C pins) DVDD33 = MIN, IOH = MAX IOH = ­0. 5 mA, DVDD33 = 3. 3 V 2. 4 0. 9DVDD33 (2) 0. 0 ­10 DVDD33 = MIN, IOL = MAX IOL = 1. 5 mA, DVDD33 = 3. 3 V IO = 3 mA 0 1. 14 VI = VSS to DVDD33 without opposing internal resistor 1. 2 0. 3 10 0. 4 0. 1DVDD33 (2) V mV V V V V mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA VOL 0. 4 1. 26 ±20 VLDO USB_VDDA1P2LDO output voltage Input current [DC] (except I2C and PCI-capable pins) VI = VSS to DVDD33 with opposing internal pullup resistor (4) VI = VSS to DVDD33 with opposing internal pulldown resistor (4) 50 ­250 100 ­100 250 ­50 ±20 ±50 II (3) Input current [DC] (I2C) VI = VSS to DVDD33 0 < VI < DVDD33 = 3. 3 V without opposing internal resistor Input current (PCI-capable pins) [DC] 0 < VI < DVDD33 = 3. 3 V with opposing internal pullup resistor (4) 0 < VI < DVDD33 = 3. 3 V with opposing internal pulldown resistor (4) GMTCLK, MTXD[7:0], MTXEN DDR2; VOH = DVDDR2 ­ 0. 4 V 50 ­250 250 ­50 ­8 ­8 ­0. 5 (2) IOH High-level output current [DC] PCI-capable pins (PCI pin function only) All other peripherals GMTCLK, MTXD[7:0], MTXEN DDR2; VOL = 0. 4 V ­4 8 8 1. 5 (2) IOL Low-level output current [DC] PCI-capable pins (PCI pin function only) All other peripherals 4 ±20 ±100 IOZ (5) I/O Off-state output current VO = DVDD33 or VSS; internal pull disabled VO = DVDD33 or VSS; internal pull enabled (1) (2) (3) (4) (5) 142 For test conditions shown as MIN, MAX, or TYP, use the appropriate value specified in the recommended operating conditions table. These rated numbers are from the PCI Local Bus Specification Revision 2. 3. The DC specifications and AC specifications are defined in Table 4-3 (DC Specifications for 3. 3V Signaling) and Table 4-4 (AC Specifications for 3. 3V Signaling), respectively. For bi-directional pins, II indicates the input leakage current and off-state (Hi-Z) output leakage current. Applies only to pins with an internal pullup (IPU) or pulldown (IPD) resistor. IOZ applies to output-only pins, indicating off-state (Hi-Z) output leakage current. Device Operating Conditions Submit Documentation Feedback Product Folder Link(s): TMS320DM6467 Copyright © 2007­2010, Texas Instruments Incorporated TMS320DM6467 www. ti. com SPRS403G ­ DECEMBER 2007 ­ REVISED OCTOBER 2010 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Temperature (Unless Otherwise Noted) (continued) PARAMETER TEST CONDITIONS (1) MIN TYP 1318. 58 MAX UNIT mA CVDD = 1. 2 V, DSP clock = 594 MHz ARM Clock = 297 MHz, DDR Clock = 297 MHz CVDD = 1. 05 V, DSP clock = 594 MHz ARM Clock = 297 MHz, DDR Clock = 297 MHz (SmartReflex V parts) CVDD = 1. 2 V, DSP clock = 594 MHz ARM Clock = 297 MHz, DDR Clock = 297 MHz (SmartReflex V parts) CVDD = 1. 2 V, DSP clock = 729 MHz ARM Clock = 364. 5 MHz, DDR Clock = 310. 5 MHz DVDD = 3. 3 V, DSP clock = 594 MHz ARM Clock = 297 MHz, DDR Clock = 297 MHz DVDD = 3. 3 V, DSP clock = 729 MHz ARM Clock = 364. 5 MHz, DDR Clock = 310. 5 MHz DVDD = 1. 8 V, DSP clock = 594 MHz ARM Clock = 297 MHz, DDR Clock = 297 MHz DVDD = 1. 8 V, DSP clock = 729 MHz ARM Clock = 364. 5 MHz, DDR Clock = 310. 5 MHz 814. 00 mA ICDD Core (CVDD, DEV_CVDD, AUX_CVDD) supply current (6) 915. 39 mA 1622. 09 mA 25. 32 mA IDDD 3. 3V I/O (DVDD33, USB_VDDA3P3) supply current (6) 26. 17 mA IDDD 1. 8V I/O (DVDDR2, PLL1VPRW18, PLL2VPRW18, DEV_DVDD18, AUX_DVDD18, USB_VDD1P8) supply current (6) 255. 15 mA 260. 42 4 4 mA pF pF CI Co Input capacitance Output capacitance (6) Measured under the following conditions: 60% DSP CPU utilization; ARM doing typical activity (peripheral configurations, other housekeeping activities); DDR2 Memory Controller at 50% utilization, 50% writes, 32 bits, 50% bit switching at room temperature (25 °C). The actual current draw varies across manufacturing processes and is highly application-dependent. For more details on core and I/O activity, as well as information relevant to board power supply design, see the TMS320DM646x Power Consumption Summary Application Report (literature number SPRAAS2). 7 Peripheral Information and Electrical Specifications 7. 1 Parameter Information Tester Pin Electronics Data Sheet Timing Reference Point 42 3. 5 nH Transmission Line Z0 = 50 (see Note) Output Under Test Device Pin (see Note) 4. 0 pF 1. 85 pF NOTE: The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects must be taken into account. A transmission line with a delay of 2 ns can be used to produce the desired transmission line effect. It is not necessary to add or subtract the transmission line delay (2 ns) from the data sheet timings. Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin. Figure 7-1. Test Load Circuit for AC Timing Measurements The load capacitance value stated is only for characterization and measurement of AC timing signals. This load capacitance value does not indicate the maximum load the device is capable of driving. Copyright © 2007­2010, Texas Instruments Incorporated Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320DM6467 143 TMS320DM6467 SPRS403G ­ DECEMBER 2007 ­ REVISED OCTOBER 2010 www. ti. com 7. 1. 1 1. . 8-V and 3. 3-V Signal Transition Levels All input and output timing parameters are referenced to Vref for both "0" and "1" logic levels. [. . . ] In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. [. . . ]