User manual TEXAS INSTRUMENTS TMS320DM6446 DATA MANUAL REV G

[. . . ] TMS320DM6446 www. ti. com SPRS283G ­ DECEMBER 2005 ­ REVISED JULY 2010 TMS320DM6446 Digital Media System-on-Chip Check for Samples: TMS320DM6446 1 Digital Media System-on-Chip (DMSoC) 1. 1 12 Features ­ 80K-Byte L1D Data RAM/Cache (2-Way Set-Associative) ­ 64K-Byte L2 Unified Mapped RAM/Cache (Flexible RAM/Cache Allocation) ARM926EJ-S Core ­ Support for 32-Bit and 16-Bit (Thumb® Mode) Instruction Sets ­ DSP Instruction Extensions and Single Cycle MAC ­ ARM® Jazelle® Technology ­ EmbeddedICE-RTTM Logic for Real-Time Debug ARM9 Memory Architecture ­ 16K-Byte Instruction Cache ­ 8K-Byte Data Cache ­ 16K-Byte RAM ­ 8K-Byte ROM Embedded Trace BufferTM (ETB11TM) With 4KB Memory for ARM9 Debug Endianness: Little Endian for ARM and DSP Video Imaging Co-Processor (VICP) Video Processing Subsystem ­ Front End Provides: · CCD and CMOS Imager Interface · BT. 601/BT. 656 Digital YCbCr 4:2:2 (8-/16-Bit) Interface · Preview Engine for Real-Time Image Processing · Glueless Interface to Common Video Decoders · Histogram Module · Auto-Exposure, Auto-White Balance and Auto-Focus Module · Resize Engine ­ Resize Images From 1/4x to 4x ­ Separate Horizontal/Vertical Control ­ Back End Provides: · Hardware On-Screen Display (OSD) · Four 54-MHz DACs for a Combination of ­ Composite NTSC/PAL Video ­ Luma/Chroma Separate Video · High-Performance Digital Media SoC ­ 513-, 594-, 810-MHz C64x+TM Clock Rates ­ 256. 5-, 297-, 405-MHz ARM926EJ-STM Clock Rates ­ Eight 32-Bit C64x+ Instructions/Cycle ­ 4104, 4752, 6480 C64x+ MIPS ­ Fully Software-Compatible With C64x / ARM9TM ­ Extended Temperature Devices Available · Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x+TM DSP Core ­ Eight Highly Independent Functional Units · Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle · Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle ­ Load-Store Architecture With Non-Aligned Support ­ 64 32-Bit General-Purpose Registers ­ Instruction Packing Reduces Code Size ­ All Instructions Conditional ­ Additional C64x+TM Enhancements · Protected Mode Operation · Exceptions Support for Error Detection and Program Redirection · Hardware Support for Modulo Loop Operation · C64x+ Instruction Set Features ­ Byte-Addressable (8-/16-/32-/64-Bit Data) ­ 8-Bit Overflow Protection ­ Bit-Field Extract, Set, Clear ­ Normalization, Saturation, Bit-Counting ­ Compact 16-Bit Instructions ­ Additional Instructions to Support Complex Multiplies · C64x+ L1/L2 Memory Architecture ­ 32K-Byte L1P Program RAM/Cache (Direct Mapped) 1 · · · · · · 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. Copyright © 2005­2010, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. TMS320DM6446 SPRS283G ­ DECEMBER 2005 ­ REVISED JULY 2010 www. ti. com · · · · · · · · · (S-video) ­ Component (YPbPr or RGB) Video (Progressive) · Digital Output ­ 8-/16-bit YUV or up to 24-Bit RGB ­ HD Resolution ­ Up to 2 Video Windows External Memory Interfaces (EMIFs) ­ 32-Bit DDR2 SDRAM Memory Controller With 256M-Byte Address Space (1. 8-V I/O) · Up to 167-MHz Controller (A-513, -594) · Up to 189-MHz Controller (-810) ­ Asynchronous16-Bit Wide EMIF (EMIFA) With 128M-Byte Address Reach · Flash Memory Interfaces ­ NOR (8-/16-Bit-Wide Data) ­ NAND (8-/16-Bit-Wide Data) Flash Card Interfaces ­ Multimedia Card (MMC)/Secure Digital (SD) with Secure Data I/O (SDIO) ­ Compact Flash Controller With True IDE Mode ­ SmartMedia Enhanced Direct-Memory-Access (EDMA3) Controller (64 Independent Channels) Two 64-Bit General-Purpose Timers (Each Configurable as Two 32-Bit Timers) One 64-Bit Watch Dog Timer Three UARTs (One with RTS and CTS Flow Control) One Serial Peripheral Interface (SPI) With Two Chip-Selects Master/Slave Inter-Integrated Circuit (I2C BusTM) Audio Serial Port (ASP) · · · · · · · · · · · · · · · · ­ I2S ­ AC97 Audio Codec Interface ­ Standard Voice Codec Interface (AIC12) 10/100 Mb/s Ethernet MAC (EMAC) ­ IEEE 802. 3 Compliant ­ Media Independent Interface (MII) VLYNQTM Interface (FPGA Interface) Host Port Interface (HPI) with 16-Bit Multiplexed Address/Data USB Port With Integrated 2. 0 PHY ­ USB 2. 0 High-/Full-Speed (480-Mbps) Client ­ USB 2. 0 High-/Full-/Low-Speed Host (Mini-Host, Supporting One External Device) Three Pulse Width Modulator (PWM) Outputs On-Chip ARM ROM Bootloader (RBL) to Boot From NAND Flash or UART ATA/ATAPI I/F (ATA/ATAPI-6 Specification) Individual Power-Saving Modes for ARM/DSP Flexible PLL Clock Generators IEEE-1149. 1 (JTAG) BoundaryScan-Compatible Up to 71 General-Purpose I/O (GPIO) Pins (Multiplexed With Other Device Functions) 361-Pin Pb-Free BGA Package (ZWT Suffix), 0. 8-mm Ball Pitch 0. 09-mm/6-Level Cu Metal Process (CMOS) 3. 3-V and 1. 8-V I/O, 1. 2-V Internal (513, 594) 3. 3-V and 1. 8-V I/O, 1. 2-V DAC and USB, 1. 3-V Internal (810 only) Applications: ­ Digital Media ­ Networked Media Encode/Decode ­ Video Imaging 1. 2 Description The TMS320DM6446 (also referenced as DM6446) leverages TI's DaVinciTM technology to meet the networked media encode and decode application processing needs of next-generation embedded devices. [. . . ] Medium bypass caps (220 nF or as large as can be obtained in a small package) should be next closest. TI recommends no less than 8 small and 8 medium caps per supply be placed immediately next to the BGA vias, using the "interior" BGA space and at least the corners of the "exterior". Larger caps for each supply can be placed further away for bulk decoupling. Large bulk caps (on the order of 100 mF) should be furthest away, but still as close as possible. Large caps for each supply should be placed outside of the BGA footprint. Any cap selection needs to be evaluated from a yield/manufacturing point-of-view. As with the selection of any component, verification of capacitor availability over the product's production lifetime should be considered. 6. 3. 1. 3 DM6446 Power and Clock Domains DM6446 includes two separate power domains: "Always On" and "DSP". The "Always On" power domain is always on when the chip is on. The "Always On" domain is powered by the VDD pins of the DM6446. The majority of the DM6446's modules lie within the "Always On" power domain. A separate domain called the "DSP" domain houses the C64x+ and VICP. The "DSP" power domain is powered by the CVDDDSP pins of the DM6446. A 27-MHz crystal is recommended for the system PLLs, which generate the internal clocks for the ARM, DSP, coprocessors, peripherals (including imaging peripherals), and EDMA3. The recommended 27-MHz input enables the use of the video DACs to drive NTSC/PAL television signals at the proper frequencies. A 24-MHz crystal is also required if the USB peripheral is to be used. For further description of the DM6446 clock domains, see Table 6-4 and Figure 6-6. 92 Peripheral and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320DM6446 Copyright © 2005­2010, Texas Instruments Incorporated TMS320DM6446 www. ti. com SPRS283G ­ DECEMBER 2005 ­ REVISED JULY 2010 Table 6-3. DM6446 Power and Clock Domains POWER DOMAIN Always On Always On Always On Always On Always On Always On Always On Always On Always On Always On Always On Always On Always On Always On Always On Always On Always On Always On Always On Always On Always On Always On Always On Always On Always On Always On Always On Always On DSP CLOCK DOMAIN CLKIN CLKIN CLKIN CLKIN CLKIN CLKIN CLKIN CLKIN CLKIN CLKIN CLKDIV2 CLKDIV3 CLKDIV3 CLKDIV3 CLKDIV3 CLKDIV6 CLKDIV6 CLKDIV6 CLKDIV6 CLKDIV6 CLKDIV6 CLKDIV6 CLKDIV6 CLKDIV6 CLKDIV6 CLKDIV6 CLKDIV6 CLKDIV6 CLKDIV1 UART0 UART1 UART2 I2C Timer0 Timer1 Timer2 PWM0 PWM1 PWM2 ARM Subsystem DDR2 VPSS EDMA3 SCR GPSC LPSCs Ice Pick EMIFA USB HPI VLYNQ EMAC ATA/CF MMC/SD/SDIO SPI ASP GPIO C64x+ CPU PERIPHERAL/MODULE Table 6-4. DM6446 Clock Domains (1) SUBSYSTEM PLL1 DSP ARM EDMA3/VPSS Peripherals (1) FIXED RATIO vs. PLL1 ­ 1:1 1:2 1:3 1:6 CLOCK MODES (FREQUENCY) PLL BYPASS 27 MHz 27 MHz 13. 5 MHz 9 MHz 4. 5 MHz PLL ENABLED ( A-513) 513 MHz 513 MHz 256. 5 MHz 171 MHz 85. 5 MHz PLL ENABLED ( -594) 594 MHz 594 MHz 297 MHz 198 MHz 99 MHz PLL ENABLED (-810) 810 MHz 810 MHz 405 MHz 270 MHz 135 MHz These table values assume a MXI/CLKIN of 27 MHz and a PLL1 multiplier equal to 22 for both A-513 and -594 devices. For -810 device, these table values assume a MXI/CLKIN of 27 MHz and a PLL1 multiplier equal to 30. Copyright © 2005­2010, Texas Instruments Incorporated Peripheral and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320DM6446 93 TMS320DM6446 SPRS283G ­ DECEMBER 2005 ­ REVISED JULY 2010 www. ti. com 27 MHz Bypass Clock SYSCLK1 PLLDIV1 (/1) SYSCLK2 PLLDIV2 (/2) PLLDIV4 (/4) PLLDIV5 (/6) PLLDIV3 (/3) PLL Controller 1 EDMA3 SYSCLK5 SYSCLK3 SCR ARM Subsystem VICP DSP Subsystem UARTs (x3) I2C PWMs (x3) Timers (x3) USB PHY 60 MHz USB 2. 0 VLYNQ EMAC 24 MHz PCLK VPFE ATA/CF EMIF/NAND MMC/SD SPI ASP PLLDIV2 (/2) BPDIV PLL Controller 2 DDR2 PHY GPIO DDR2 VTP DDR2 Mem Ctlr HPI ARM INTC VPBECLK VPBE DACs PLLDIV1 (/1) Figure 6-6. PLL1 and PLL2 Clock Domain Block Diagram For further detail on PLL1 and PLL2, see the structure block diagrams Figure 6-7 and Figure 6-8, respectively. CLKMODE PLLEN CLKIN OSCIN 1 PLL 0 0 PLLM PLLDIV4 (/4) PLLDIV5 (/6) SYSCLK4 SYSCLK5 AUXCLK BPDIV SYSCLKBP Post-DIV 1 PLLDIV3 (/3) SYSCLK3 PLLDIV1 (/1) PLLDIV2 (/2) SYSCLK1 SYSCLK2 Figure 6-7. [. . . ] In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. [. . . ]