User manual TEXAS INSTRUMENTS TMS320DM335 DATA MANUAL REV C

[. . . ] TMS320DM335 www. ti. com SPRS528C ­ JULY 2008 ­ REVISED JUNE 2010 TMS320DM335 Digital Media System-on-Chip (DMSoC) Check for Samples: TMS320DM335 1 Digital Media System-on-Chip (DMSoC) 1. 1 123 TMS320DM335 Features ­ EmbeddedICE-RTTM Logic for Real-Time Debug ARM9 Memory Architecture ­ 16K-Byte Instruction Cache ­ 8K-Byte Data Cache ­ 32K-Byte RAM ­ 8K-Byte ROM ­ Little Endian Video Processing Subsystem ­ Front End Provides: · Hardware IPIPE for Real-Time Image Processing · Up to 14-bit CCD/CMOS Digital Interface · 16-/8-bit Generic YcBcR-4:2 Interface (BT. 601) · 10-/8-bit CCIR6565/BT655 Interface · Up to 75-MHz Pixel Clock · Histogram Module · Resize Engine ­ Resize Images From 1/16x to 8x ­ Separate Horizontal/Vertical Control ­ Two Simultaneous Output Paths ­ Back End Provides: · Hardware On-Screen Display (OSD) · Composite NTSC/PAL video encoder output · 8-/16-bit YCC and Up to 18-Bit RGB666 Digital Output · BT. 601/BT. 656 Digital YCbCr 4:2:2 (8-/16-Bit) Interface · Digital HDTV (720p/1080i) output for connection to external encoder External Memory Interfaces (EMIFs) ­ DDR2 and mDDR SDRAM 16-bit wide EMIF With 256 MByte Address Space (1. 8-V I/O) ­ Asynchronous16-/8-bit Wide EMIF (AEMIF) · Flash Memory Interfaces ­ NAND (8-/16-bit Wide Data) ­ OneNAND(16-bit Wide Data) Flash Card Interfaces · Highlights ­ High-Performance Digital Media System-On-Chip (DMSoC) ­ Up to 216-MHz ARM926EJ-STM Clock Rate ­ Digital HDTV (720p/1080i) output for connection to external encoder ­ Video Processing Subsystem · Hardware IPIPE for Real-Time Image Processing · Up to 14-bit CCD/CMOS Digital Interface · Histogram Module · Resize Image 1/16x to 8x · Hardware On-Screen Display · Up to 75-MHz Pixel Clock · Composite NTSC/PAL video encoder output ­ Peripherals include DDR and mDDR SDRAM, 2 MMC/SD/SDIO and SmartMedia Flash Card Interfaces, USB 2. 0, 3 UARTs and 3 SPIs ­ Enhanced Direct-Memory-Access (EDMA) ­ Configurable Power-Saving Modes ­ On-Chip ARM ROM Bootloader (RBL) to Boot From NAND Flash, MMC/SD, or UART ­ 3. 3-V and 1. 8-V I/O, 1. 3-V Core ­ Debug Interface Support ­ Up to 104 General-Purpose I/O (GPIO) Pins ­ 337-Pin Ball Grid Array at 65 nm Process Technology · High-Performance Digital Media System-on-Chip (DMSoC) ­ 135-, 216-MHz ARM926EJ-STM Clock Rate ­ Fully Software-Compatible With ARMTM ­ Extended Temperature 135- and 216-MHz Devices are Available · ARM926EJ-S Core ­ Support for 32-Bit and 16-Bit (Thumb Mode) Instruction Sets ­ DSP Instruction Extensions and Single Cycle MAC ­ ARM® Jazelle® Technology 1 · · · · 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All other trademarks are the property of their respective owners. Copyright © 2008­2010, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. TMS320DM335 SPRS528C ­ JULY 2008 ­ REVISED JUNE 2010 www. ti. com · · · · · · · · ­ Two Multimedia Card (MMC) / Secure Digital (SD/SDIO) ­ SmartMedia Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels) USB Port with Integrated 2. 0 High-Speed PHY that Supports ­ USB 2. 0 Full and High-Speed Device ­ USB 2. 0 Low, Full, and High-Speed Host Three 64-Bit General-Purpose Timers (each configurable as two 32-bit timers) One 64-Bit Watch Dog Timer Three UARTs (One fast UART with RTS and CTS Flow Control) Three Serial Port Interfaces (SPI) each with two Chip-Selects One Master/Slave Inter-Integrated Circuit (I2C) Bus® Two Audio Serial Port (ASP) ­ I2S and TDM I2S ­ AC97 Audio Codec Interface ­ S/PDIF via Software ­ Standard Voice Codec Interface (AIC12) ­ SPI Protocol (Master Mode Only) · Four Pulse Width Modulator (PWM) Outputs · Four RTO (Real Time Out) Outputs · Up to 104 General-Purpose I/O (GPIO) Pins (Multiplexed with Other Device Functions) · On-Chip ARM ROM Bootloader (RBL) to Boot from NAND Flash (with SPI EEPROM Boot option), MMC/SD, or UART · Configurable Power-Saving Modes · Crystal or External Clock Input (typically 24 MHz or 36 MHz) · Flexible PLL Clock Generators · Debug Interface Support ­ IEEE-1149. 1 (JTAG) Boundary-Scan-Compatible ­ ETBTM (Embedded Trace BufferTM) with 4K-Bytes Trace Buffer memory ­ Device Revision ID Readable by ARM · 337-Pin Ball Grid Array (BGA) Package (ZCE Suffix), 0. 65-mm Ball Pitch · 90nm Process Technology · 3. 3-V and 1. 8-V I/O, 1. 3-V Internal · Community Resources ­ TI E2E Community ­ TI Embedded Processors Wiki 2 Digital Media System-on-Chip (DMSoC) Submit Documentation Feedback Product Folder Link(s): TMS320DM335 Copyright © 2008­2010, Texas Instruments Incorporated TMS320DM335 www. ti. com SPRS528C ­ JULY 2008 ­ REVISED JUNE 2010 1. 2 Description The DM335 processor is a low-cost, low-power processor providing advanced graphical user interface for display applications that do not require video compression and decompression. [. . . ] After the AEMIF module is configured, booting will continue immediately after the OneNAND's boot page with the AEMIF module managing pages thereafter. · The RBL supports 3 distinct boot modes: ­ BTSEL[1:0] = 00 - ARM NAND/SPI Boot ­ BTSEL[1:0] = 10 - ARM MMC/SD Boot ­ BTSEL[1:0] = 11 - ARM UART Boot · In NAND mode if SPI boot fails, then NAND mode is tried. · RBL uses GIO61 to indicate boot status (can use to blink LED): ­ After reset, GIO61 is initially driven low (e. g LED off) ­ If NAND boot fails, then GIO61 shall toggle at 4Hz while MMC/SD boot is tried. ­ If MMC/SD boot fails, then GIO61 shall toggle at 4Hz while MMC/SD boot is retried. ­ If UART boot fails, then GIO61 shall toggle at 2Hz while UART boot is retried. ­ When boot is successful, just before program control is given to UBL, GIO61 is driven high (e. g. ­ DM335 Timer0 shall be used to accurately toggle GIO61 at 4Hz and 2Hz. · ARM ROM Boot - SPI boot in NAND Mode ­ No support for a full firmware boot. Instead, copies a second stage User Boot Loader (UBL) from SPI to ARM Internal RAM (AIM) and transfers control to the user software. ­ Support for 16 and 24 bit SPI EEPROMs ­ Support for up to 30KB UBL (32KB - ~2KB for RBL stack) ­ RBL will copy UBL to ARM Internal RAM (AIM) via SPI interface from a SPI peripheral like SPI EEPROM. · ARM ROM Boot - NAND Mode (See Section 3. 12. 2 for a full explanation of the differences between Standard Mode and Compatibility Mode. ): ­ No support for a full firmware boot. Instead, copies a second stage User Boot Loader (UBL) from NAND flash to ARM internal RAM (AIM) and transfers control to the user-defined UBL ­ Support for NAND with page sizes up to 8192 bytes in Standard Mode and 2048 bytes in Compatibility Mode Note: At the time of documentation for this device, 8192-byte devices were not available for testing. The code does contain support for these devices; however, it has not yet been tested. ­ Support for magic number error detection and retry (up to 24 times) when loading UBL ­ Support for up to 30KB UBL (32KB IRAM - ~2KB for RBL stack) Copyright © 2008­2010, Texas Instruments Incorporated Detailed Device Description Submit Documentation Feedback Product Folder Link(s): TMS320DM335 85 TMS320DM335 SPRS528C ­ JULY 2008 ­ REVISED JUNE 2010 www. ti. com · · ­ Optional, user-selectable, support for use of DMA and I-cache during RBL execution (i. e. , while loading UBL) ­ Supports booting from 8-bit NAND devices (16-bit NAND devices are not supported) ­ Uses/Requires 4-bit HW ECC (NAND devices with ECC requirements 4 bits per 512 bytes are supported) ­ Supports NAND flash that requires chip select to stay low during the tR read time Notes: ­ See Section 3. 12. 2 for a full explanation of the differences between Standard Mode and Compatibility Mode. ­ The GIO000 pin must be held high during NAND boot for the boot process to fuction properly. Instead, copies a second stage User Boot Loader (UBL) from MMC/SD to ARM Internal RAM (AIM) and transfers control to the user software. ­ Support for MMC/SD Native protocol (MMC/SD SPI protocol is not supported) ­ Support for descriptor error detection and retry (up to 24 times) when loading UBL ­ Support for up to 30KB UBL (32KB - ~2KB for RBL stack) ARM ROM Boot - UART mode ­ No support for a full firmware boot. Instead, loads a second stage User Boot Loader (UBL) via UART to ARM internal RAM (AIM) and transfers control to the user software. ­ Support for up to 30KB UBL (32KB - ~2KB for RBL stack) The general boot sequence is shown in Figure 3-6. For more information, refer to the TMS320DM335 Digital Media System-on-Chip (DMSoC) ARM Subsystem Reference Guide (literature number SPRUFX7). 86 Detailed Device Description Submit Documentation Feedback Product Folder Link(s): TMS320DM335 Copyright © 2008­2010, Texas Instruments Incorporated TMS320DM335 www. ti. com SPRS528C ­ JULY 2008 ­ REVISED JUNE 2010 Reset Boot mode ?No Yes Boot from MMC/SD Boot OK ? No Yes Invoke OneNAND Invoke loaded Program Figure 3-6. Boot Mode Functional Block Diagram 3. 12. 2 RBL NAND Boot Process The RBL NAND boot process is described as follows: · Upon NAND boot, if a SPI EEPROM is present, RBL reads first 32 bytes and look for magic pattern at offset 0x8. [. . . ] In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. [. . . ]