User manual TEXAS INSTRUMENTS TMS320C6748 DATASHEET 08-2010

[. . . ] TMS320C6748 www. ti. com SPRS590B ­ JUNE 2009 ­ REVISED AUGUST 2010 TMS320C6748 Fixed/Floating-Point DSP Check for Samples: TMS320C6748 1 TMS320C6748 Fixed/Floating-Point DSP 1. 1 12 Features Support ­ 64 General-Purpose Registers (32 Bit) ­ Six ALU (32-/40-Bit) Functional Units · Supports 32-Bit Integer, SP (IEEE Single Precision/32-Bit) and DP (IEEE Double Precision/64-Bit) Floating Point · Supports up to Four SP Additions Per Clock, Four DP Additions Every 2 Clocks · Supports up to Two Floating Point (SP or DP) Reciprocal Approximation (RCPxP) and Square-Root Reciprocal Approximation (RSQRxP) Operations Per Cycle ­ Two Multiply Functional Units · Mixed-Precision IEEE Floating Point Multiply Supported up to: ­ 2 SP x SP -> SP Per Clock ­ 2 SP x SP -> DP Every Two Clocks ­ 2 SP x DP -> DP Every Three Clocks ­ 2 DP x DP -> DP Every Four Clocks · Fixed Point Multiply Supports Two 32 x 32-Bit Multiplies, Four 16 x 16-Bit Multiplies, or Eight 8 x 8-Bit Multiplies per Clock Cycle, and Complex Multiples ­ Instruction Packing Reduces Code Size ­ All Instructions Conditional ­ Hardware Support for Modulo Loop Operation ­ Protected Mode Operation ­ Exceptions Support for Error Detection and Program Redirection Software Support ­ TI DSP/BIOSTM ­ Chip Support Library and DSP Library 128K-Byte RAM Memory 1. 8V or 3. 3V LVCMOS IOs (except for USB and DDR2 interfaces) Two External Memory Interfaces: ­ EMIFA · NOR (8-/16-Bit-Wide Data) · NAND (8-/16-Bit-Wide Data) · 16-Bit SDRAM With 128 MB Address Space · Highlights ­ 375/456-MHz C674x Fixed/Floating-Point VLIW DSP ­ Enhanced Direct-Memory-Access Controller (EDMA3) ­ Serial ATA (SATA) Controller ­ DDR2/Mobile DDR Memory Controller ­ Two Multimedia Card (MMC)/Secure Digital (SD) Card Interface ­ LCD Controller ­ Video Port Interface (VPIF) ­ 10/100 Mb/s Ethernet MAC (EMAC): ­ Programmable Real-Time Unit Subsystem ­ Three Configurable UART Modules ­ USB 1. 1 OHCI (Host) With Integrated PHY ­ USB 2. 0 OTG Port With Integrated PHY ­ One Multichannel Audio Serial Port ­ Two Multichannel Buffered Serial Ports · 375/456-MHz C674x VLIW DSP · C674x Instruction Set Features ­ Superset of the C67x+TM and C64x+TM ISAs ­ Up to 3648/2746 C674x MIPS/MFLOPS ­ Byte-Addressable (8-/16-/32-/64-Bit Data) ­ 8-Bit Overflow Protection ­ Bit-Field Extract, Set, Clear ­ Normalization, Saturation, Bit-Counting ­ Compact 16-Bit Instructions · C674x Two Level Cache Memory Architecture ­ 32K-Byte L1P Program RAM/Cache ­ 32K-Byte L1D Data RAM/Cache ­ 256K -Byte L2 Unified Mapped RAM/Cache ­ Flexible RAM/Cache Partition (L1 and L2) · Enhanced Direct-Memory-Access Controller 3 (EDMA3): ­ 2 Channel Controllers ­ 3 Transfer Controllers ­ 64 Independent DMA Channels ­ 16 Quick DMA Channels ­ Programmable Transfer Burst Size · TMS320C674x Floating-Point VLIW DSP Core ­ Load-Store Architecture With Non-Aligned 1 · · · · 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. TMS320C6000, C6000 are trademarks of Texas Instruments. Copyright © 2009­2010, Texas Instruments Incorporated ADVANCE INFORMATION concerns new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice. ADVANCE INFORMATION TMS320C6748 SPRS590B ­ JUNE 2009 ­ REVISED AUGUST 2010 www. ti. com · · · · · · · · · · · ­ DDR2/Mobile DDR Memory Controller · 16-Bit DDR2 SDRAM With 512 MB Address Space or · 16-Bit mDDR SDRAM With 256 MB Address Space Three Configurable 16550 type UART Modules: ­ With Modem Control Signals ­ 16-byte FIFO ­ 16x or 13x Oversampling Option LCD Controller Two Serial Peripheral Interfaces (SPI) Each With Multiple Chip-Selects Two Multimedia Card (MMC)/Secure Digital (SD) Card Interface with Secure Data I/O (SDIO) Interfaces Two Master/Slave Inter-Integrated Circuit (I2C BusTM) One Host-Port Interface (HPI) With 16-Bit-Wide Muxed Address/Data Bus For High Bandwidth Programmable Real-Time Unit Subsystem (PRUSS) ­ Two Independent Programmable Realtime Unit (PRU) Cores · 32-Bit Load/Store RISC architecture · 4K Byte instruction RAM per core · 512 Bytes data RAM per core · PRU Subsystem (PRUSS) can be disabled via software to save power · Register 30 of each PRU is exported from the subsystem in addition to the normal R31 output of the PRU cores. ­ Standard power management mechanism · Clock gating · Entire subsystem under a single PSC clock gating domain ­ Dedicated interrupt controller ­ Dedicated switched central resource USB 1. 1 OHCI (Host) With Integrated PHY (USB1) USB 2. 0 OTG Port With Integrated PHY (USB0) ­ USB 2. 0 High-/Full-Speed Client ­ USB 2. 0 High-/Full-/Low-Speed Host ­ End Point 0 (Control) ­ End Points 1, 2, 3, 4 (Control, Bulk, Interrupt or ISOC) Rx and Tx One Multichannel Audio Serial Port: ­ Two Clock Zones and 16 Serial Data Pins ­ Supports TDM, I2S, and Similar Formats ­ DIT-Capable ­ FIFO buffers for Transmit and Receive Two Multichannel Buffered Serial Ports: ­ Supports TDM, I2S, and Similar Formats ­ AC97 Audio Codec Interface TMS320C6748 Fixed/Floating-Point DSP · · · · · · · · · · ­ Telecom Interfaces (ST-Bus, H100) ­ 128-channel TDM ­ FIFO buffers for Transmit and Receive 10/100 Mb/s Ethernet MAC (EMAC): ­ IEEE 802. 3 Compliant ­ MII Media Independent Interface ­ RMII Reduced Media Independent Interface ­ Management Data I/O (MDIO) Module Video Port Interface (VPIF): ­ Two 8-bit SD (BT. 656), Single 16-bit or Single Raw (8-/10-/12-bit) Video Capture Channels ­ Two 8-bit SD (BT. 656), Single 16-bit Video Display Channels Universal Parallel Port (uPP): ­ High-Speed Parallel Interface to FPGAs and Data Converters ­ Data Width on Each of Two Channels is 8- to 16-bit Inclusive ­ Single Data Rate or Dual Data Rate Transfers ­ Supports Multiple Interfaces with START, ENABLE and WAIT Controls Serial ATA (SATA) Controller: ­ Supports SATA I (1. 5 Gbps) and SATA II (3. 0 Gbps) ­ Supports all SATA Power Management Features ­ Hardware-Assisted Native Command Queueing (NCQ) for up to 32 Entries ­ Supports Port Multiplier and Command-Based Switching Real-Time Clock With 32 KHz Oscillator and Separate Power Rail Three 64-Bit General-Purpose Timers (Each configurable as Two 32-Bit Timers) One 64-bit General-Purpose/Watchdog Timer (Configurable as Two 32-bit General-Purpose Timers) Two Enhanced Pulse Width Modulators (eHRPWM): ­ Dedicated 16-Bit Time-Base Counter With Period And Frequency Control ­ 6 Single Edge, 6 Dual Edge Symmetric or 3 Dual Edge Asymmetric Outputs ­ Dead-Band Generation ­ PWM Chopping by High-Frequency Carrier ­ Trip Zone Input Three 32-Bit Enhanced Capture Modules (eCAP): ­ Configurable as 3 Capture Inputs or 3 Auxiliary Pulse Width Modulator (APWM) outputs ­ Single Shot Capture of up to Four Event Time-Stamps 361-Ball Pb-Free Plastic Ball Grid Array (PBGA) Copyright © 2009­2010, Texas Instruments Incorporated ADVANCE INFORMATION 2 Submit Documentation Feedback Product Folder Link(s): TMS320C6748 TMS320C6748 www. ti. com SPRS590B ­ JUNE 2009 ­ REVISED AUGUST 2010 [ZCE Suffix], 0. 65-mm Ball Pitch · 361-Ball Pb-Free Plastic Ball Grid Array (PBGA) [ZWT Suffix], 0. 80-mm Ball Pitch · Commercial, Extended or Industrial Temperature · Community Resources ­ TI E2E Community ­ TI Embedded Processors Wiki Copyright © 2009­2010, Texas Instruments Incorporated TMS320C6748 Fixed/Floating-Point DSP Submit Documentation Feedback Product Folder Link(s): TMS320C6748 3 ADVANCE INFORMATION TMS320C6748 SPRS590B ­ JUNE 2009 ­ REVISED AUGUST 2010 www. ti. com 1. 2 Trademarks DSP/BIOS, TMS320C6000, C6000, TMS320, TMS320C62x, and TMS320C67x are trademarks of Texas Instruments. [. . . ] There is no need and it is not recommended to skew match across data bytes, i. e. , from DQS0 and data byte 0 to DQS1 and data byte 1. DQLM is the longest Manhattan distance of each of the DQS and D net class. 132 Peripheral Information and Electrical Specifications Copyright © 2009­2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320C6748 TMS320C6748 www. ti. com SPRS590B ­ JUNE 2009 ­ REVISED AUGUST 2010 Figure 6-25 shows the routing for the DQGATE net class. Table 6-36 contains the routing specification. A1 T A1 Figure 6-25. 1 2 3 4 (1) (2) (3) Parameter DQGATE Length F Center to center DQGATE to any other trace spacing DQS/D nominal trace length DQGATE Skew CKB0B1 is the sum of the length of the CK net plus the average length of the DQS0 and DQS1 nets. w = PCB trace width as defined in Table 6-27 Skew from CKB0B1 4w (2) DDR2/mDDR Controller F T Min Typ CKB0B1 Max Unit Notes See Note (1) DQLM-50 DQLM DQLM+50 100 Mils Mils See Note (3) 6. 11. 3. 12 MDDR/DDR2 Boundary Scan Limitations Due to DDR implementation and timing restrictions, it was not possible to place boundary scan cells between core logic and the IO like boundary scan cells for other IO. Instead, the boundary scan cells are tapped-off to the DDR PHY and there is the equivalent of a multiplexer inside the DDR PHY which selects between functional and boundary scan paths. The implication for boundary scan is that the DDR pins will not support the SAMPLE function of the output enable cells on the DDR pins and this is a violation of IEEE 1149. 1. Full EXTEST and PRELOAD capability is still available. Copyright © 2009­2010, Texas Instruments Incorporated Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320C6748 133 ADVANCE INFORMATION TMS320C6748 SPRS590B ­ JUNE 2009 ­ REVISED AUGUST 2010 www. ti. com 6. 12 Memory Protection Units The MPU performs memory protection checking. It receives requests from a bus master in the system and checks the address against the fixed and programmable regions to see if the access is allowed. If allowed, the transfer is passed unmodified to its output bus (to the targeted address). If the transfer is illegal (fails the protection check) then the MPU does not pass the transfer to the output bus but rather services the transfer internally back to the input bus (to prevent a hang) returning the fault status to the requestor as well as generating an interrupt about the fault. The following features are supported by the MPU: · Provides memory protection for fixed and programmable address ranges. · Generates an interrupt when there is a protection violation, and saves violating transfer parameters. MPU1 Configuration Registers ADVANCE INFORMATION MPU1 BYTE ADDRESS 0x01E1 4000 0x01E1 4004 0x01E1 4010 0x01E1 4014 0x01E1 4018 0x01E1 401C 0x01E1 4020 - 0x01E1 41FF 0x01E1 4200 0x01E1 4204 0x01E1 4208 0x01E1 420C - 0x01E1 420F 0x01E1 4210 0x01E1 4214 0x01E1 4218 0x01E1 421C - 0x01E1 421F 0x01E1 4220 0x01E1 4224 0x01E1 4228 0x01E1 422C - 0x01E1 422F 0x01E1 4230 0x01E1 4234 0x01E1 4238 0x01E1 423C - 0x01E1 423F 0x01E1 4240 0x01E1 4244 0x01E1 4248 0x01E1 424C - 0x01E1 424F 0x01E1 4250 0x01E1 4254 0x01E1 4258 0x01E1 425C - 0x01E1 42FF 134 ACRONYM REVID CONFIG IRAWSTAT IENSTAT IENSET IENCLR PROG1_MPSAR PROG1_MPEAR PROG1_MPPA PROG2_MPSAR PROG2_MPEAR PROG2_MPPA PROG3_MPSAR PROG3_MPEAR PROG3_MPPA PROG4_MPSAR PROG4_MPEAR PROG4_MPPA PROG5_MPSAR PROG5_MPEAR PROG5_MPPA PROG6_MPSAR PROG6_MPEAR PROG6_MPPA Revision ID Configuration Interrupt raw status/set REGISTER DESCRIPTION Interrupt enable status/clear Interrupt enable Interrupt enable clear Reserved Programmable range 1, start address Programmable range 1, end address Programmable range 1, memory page protection attributes Reserved Programmable range 2, start address Programmable range 2, end address Programmable range 2, memory page protection attributes Reserved Programmable range 3, start address Programmable range 3, end address Programmable range 3, memory page protection attributes Reserved Programmable range 4, start address Programmable range 4, end address Programmable range 4, memory page protection attributes Reserved Programmable range 5, start address Programmable range 5, end address Programmable range 5, memory page protection attributes Reserved Programmable range 6, start address Programmable range 6, end address Programmable range 6, memory page protection attributes Reserved Peripheral Information and Electrical Specifications Copyright © 2009­2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320C6748 TMS320C6748 www. ti. com SPRS590B ­ JUNE 2009 ­ REVISED AUGUST 2010 Table 6-37. MPU1 Configuration Registers (continued) MPU1 BYTE ADDRESS 0x01E1 4300 0x01E1 4304 0x01E1 4308 0x01E1 430C - 0x01E1 4FFF ACRONYM FLTADDRR FLTSTAT FLTCLR Fault address Fault status Fault clear Reserved REGISTER DESCRIPTION Table 6-38. MPU2 Configuration Registers MPU1 BYTE ADDRESS 0x01E1 5000 0x01E1 5004 0x01E1 5010 0x01E1 5014 0x01E1 5018 0x01E1 501C 0x01E1 5020 - 0x01E1 50FF 0x01E1 5100 0x01E1 5104 0x01E1 5108 0x01E1 510C - 0x01E1 51FF 0x01E1 5200 0x01E1 5204 0x01E1 5208 0x01E1 520C - 0x01E1 520F 0x01E1 5210 0x01E1 5214 0x01E1 5218 0x01E1 521C - 0x01E1 521F 0x01E1 5220 0x01E1 5224 0x01E1 5228 0x01E1 522C - 0x01E1 522F 0x01E1 5230 0x01E1 5234 0x01E1 5238 0x01E1 523C - 0x01E1 523F 0x01E1 5240 0x01E1 5244 0x01E1 5248 0x01E1 524C - 0x01E1 524F 0x01E1 5250 0x01E1 5254 0x01E1 5258 0x01E1 525C - 0x01E1 525F 0x01E1 5260 0x01E1 5264 0x01E1 5268 0x01E1 526C - 0x01E1 526F ACRONYM REVID CONFIG IRAWSTAT IENSTAT IENSET IENCLR FXD_MPSAR FXD_MPEAR FXD_MPPA PROG1_MPSAR PROG1_MPEAR PROG1_MPPA PROG2_MPSAR PROG2_MPEAR PROG2_MPPA PROG3_MPSAR PROG3_MPEAR PROG3_MPPA PROG4_MPSAR PROG4_MPEAR PROG4_MPPA PROG5_MPSAR PROG5_MPEAR PROG5_MPPA PROG6_MPSAR PROG6_MPEAR PROG6_MPPA PROG7_MPSAR PROG7_MPEAR PROG7_MPPA Revision ID Configuration Interrupt raw status/set Interrupt enable status/clear Interrupt enable Reserved Fixed range start address Fixed range end start address Fixed range memory page protection attributes Reserved Programmable range 1, start address Programmable range 1, end address Programmable range 1, memory page protection attributes Reserved Programmable range 2, start address Programmable range 2, end address Programmable range 2, memory page protection attributes Reserved Programmable range 3, start address Programmable range 3, end address Programmable range 3, memory page protection attributes Reserved Programmable range 4, start address Programmable range 4, end address Programmable range 4, memory page protection attributes Reserved Programmable range 5, start address Programmable range 5, end address Programmable range 5, memory page protection attributes Reserved Programmable range 6, start address Programmable range 6, end address Programmable range 6, memory page protection attributes Reserved Programmable range 7, start address Programmable range 7, end address Programmable range 7, memory page protection attributes Reserved Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320C6748 135 Interrupt enable clear REGISTER DESCRIPTION Copyright © 2009­2010, Texas Instruments Incorporated ADVANCE INFORMATION TMS320C6748 SPRS590B ­ JUNE 2009 ­ REVISED AUGUST 2010 www. ti. com Table 6-38. MPU2 Configuration Registers (continued) MPU1 BYTE ADDRESS 0x01E1 5270 0x01E1 5274 0x01E1 5278 0x01E1 527C - 0x01E1 527F 0x01E1 5280 0x01E1 5284 0x01E1 5288 0x01E1 528C - 0x01E1 528F 0x01E1 5290 0x01E1 5294 0x01E1 5298 0x01E1 529C - 0x01E1 529F 0x01E1 52A0 0x01E1 52A4 0x01E1 52A8 0x01E1 52AC - 0x01E1 52AF 0x01E1 52B0 0x01E1 52B4 0x01E1 52B8 0x01E1 52BC - 0x01E1 52FF 0x01E1 5300 0x01E1 5304 0x01E1 5308 0x01E1 530C - 0x01E1 5FFF ACRONYM PROG8_MPSAR PROG8_MPEAR PROG8_MPPA PROG9_MPSAR PROG9_MPEAR PROG9_MPPA PROG10_MPSAR PROG10_MPEAR PROG10_MPPA PROG11_MPSAR PROG11_MPEAR PROG11_MPPA PROG12_MPSAR PROG12_MPEAR PROG12_MPPA FLTADDRR FLTSTAT FLTCLR REGISTER DESCRIPTION Programmable range 8, start address Programmable range 8, end address Programmable range 8, memory page protection attributes Reserved Programmable range 9, start address Programmable range 9, end address Programmable range 9, memory page protection attributes Reserved Programmable range 10, start address Programmable range 10, end address Programmable range 10, memory page protection attributes Reserved Programmable range 11, start address Programmable range 11, end address Programmable range 11, memory page protection attributes Reserved Programmable range 12, start address Programmable range 12, end address Programmable range 12, memory page protection attributes Reserved Fault address Fault status Fault clear Reserved ADVANCE INFORMATION 136 Peripheral Information and Electrical Specifications Copyright © 2009­2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320C6748 TMS320C6748 www. ti. com SPRS590B ­ JUNE 2009 ­ REVISED AUGUST 2010 6. 13 MMC / SD / SDIO (MMCSD0, MMCSD1) 6. 13. 1 MMCSD Peripheral Description The device includes an two MMCSD controllers which are compliant with MMC V4. 0, Secure Digital Part 1 Physical Layer Specification V1. 1 and Secure Digital Input Output (SDIO) V2. 0 specifications. The MMC/SD Controller have following features: · MultiMediaCard (MMC). The device MMC/SD Controller does not support SPI mode. 6. 13. 2 MMCSD Peripheral Register Description(s) Table 6-39. Multimedia Card/Secure Digital (MMC/SD) Card Controller Registers MMCSD0 BYTE ADDRESS 0x01C4 0000 0x01C4 0004 0x01C4 0008 0x01C4 000C 0x01C4 0010 0x01C4 0014 0x01C4 0018 0x01C4 001C 0x01C4 0020 0x01C4 0024 0x01C4 0028 0x01C4 002C 0x01C4 0030 0x01C4 0034 0x01C4 0038 0x01C4 003C 0x01C4 0040 0x01C4 0044 0x01C4 0048 0x01C4 0050 0x01C4 0064 0x01C4 0068 0x01C4 006C 0x01C4 0070 0x01C4 0074 MMCSD1 BYTE ADDRESS 0x01E1 B000 0x01E1 B004 0x01E1 B008 0x01E1 B00C 0x01E1 B010 0x01E1 B014 0x01E1 B018 0x01E1 B01C 0x01E1 B020 0x01E1 B024 0x01E1 B028 0x01E1 B02C 0x01E1 B030 0x01E1 B034 0x01E1 B038 0x01E1 B03C 0x01E1 B040 0x01E1 B044 0x01E1 B048 0x01E1 B050 0x01E1 B064 0x01E1 B068 0x01E1 B06C 0x01E1 B070 0x01E1 B074 ACRONYM MMCCTL MMCCLK MMCST0 MMCST1 MMCIM MMCTOR MMCTOD MMCBLEN MMCNBLK MMCNBLC MMCDRR MMCDXR MMCCMD MMCARGHL MMCRSP01 MMCRSP23 MMCRSP45 MMCRSP67 MMCDRSP MMCCIDX SDIOCTL SDIOST0 SDIOIEN SDIOIST MMCFIFOCTL MMC Control Register REGISTER DESCSRIPTION MMC Memory Clock Control Register MMC Status Register 0 MMC Status Register 1 MMC Interrupt Mask Register MMC Response Time-Out Register MMC Data Read Time-Out Register MMC Block Length Register MMC Number of Blocks Register MMC Number of Blocks Counter Register MMC Data Receive Register MMC Data Transmit Register MMC Command Register MMC Argument Register MMC Response Register 0 and 1 MMC Response Register 2 and 3 MMC Response Register 4 and 5 MMC Response Register 6 and 7 MMC Data Response Register MMC Command Index Register SDIO Control Register SDIO Status Register 0 SDIO Interrupt Enable Register SDIO Interrupt Status Register MMC FIFO Control Register Copyright © 2009­2010, Texas Instruments Incorporated Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320C6748 137 ADVANCE INFORMATION TMS320C6748 SPRS590B ­ JUNE 2009 ­ REVISED AUGUST 2010 www. ti. com 6. 13. 3 MMC/SD Electrical Data/Timing Table 6-40 through Table 6-41 assume testing over recommended operating conditions. 1 2 3 4 PARAMETER tsu(CMDV-CLKH) Setup time, MMCSD_CMD valid before MMCSD_CLK high th(CLKH-CMDV) tsu(DATV-CLKH) th(CLKH-DATV) Hold time, MMCSD_CMD valid after MMCSD_CLK high Setup time, MMCSD_DATx valid before MMCSD_CLK high Hold time, MMCSD_DATx valid after MMCSD_CLK high 1. 3V, 1. 2V MIN 4 2. 5 4. 5 2. 5 MAX 4 2. 5 5 2. 5 1. 1V MIN MAX 6 2. 5 6 2. 5 1. 0V MIN MAX UNIT ns ns ns ns Table 6-41. Switching Characteristics for MMC/SD (see Figure 6-26 through Figure 6-29) NO. [. . . ] In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. [. . . ]