User manual TEXAS INSTRUMENTS TMS320C6455 DATASHEET 09-2010

[. . . ] TMS320C6455 www. ti. com SPRS276J ­ MAY 2005 ­ REVISED SEPTEMBER 2010 TMS320C6455 Fixed-Point Digital Signal Processor Check for Samples: TMS320C6455 1 Features 12 · High-Performance Fixed-Point DSP (C6455) ­ 1. 39-, 1. 17-, 1-, and 0. 83-ns Instruction Cycle Time ­ 720-MHz, 850-MHz, 1-GHz, and 1. 2-GHz Clock Rate ­ Eight 32-Bit Instructions/Cycle ­ 9600 MIPS/MMACS (16-Bits) ­ Commercial Temperature [0°C to 90°C] ­ Extended Temperature [-40°C to 105°C] · TMS320C64x+TM DSP Core ­ Dedicated SPLOOP Instruction ­ Compact Instructions (16-Bit) ­ Instruction Set Enhancements ­ Exception Handling · TMS320C64x+ Megamodule L1/L2 Memory Architecture: ­ 256K-Bit (32K-Byte) L1P Program Cache [Direct Mapped] ­ 256K-Bit (32K-Byte) L1D Data Cache [2-Way Set-Associative] ­ 16M-Bit (2048K-Byte) L2 Unified Mapped RAM/Cache [Flexible Allocation] ­ 256K-Bit (32K-Byte) L2 ROM ­ Time Stamp Counter · Enhanced Viterbi Decoder Coprocessor (VCP2) ­ Supports Over 694 7. 95-Kbps AMR ­ Programmable Code Parameters · Enhanced Turbo Decoder Coprocessor (TCP2) ­ Supports up to Eight 2-Mbps 3GPP (6 Iterations) ­ Programmable Turbo Code and Decoding Parameters · Endianess: Little Endian, Big Endian · 64-Bit External Memory Interface (EMIFA) ­ Glueless Interface to Asynchronous Memories (SRAM, Flash, and EEPROM) and Synchronous Memories (SBSRAM, ZBT SRAM) ­ Supports Interface to Standard Sync Devices and Custom Logic (FPGA, CPLD, ASICs, etc. ) ­ 32M-Byte Total Addressable External Memory Space 1 · Four 1x Serial RapidIO® Links (or One 4x), v1. 2 Compliant ­ 1. 25-, 2. 5-, 3. 125-Gbps Link Rates ­ Message Passing, DirectIO Support, Error Mgmt Extensions, Congestion Control ­ IEEE 1149. 6 Compliant I/Os · DDR2 Memory Controller ­ Interfaces to DDR2-533 SDRAM ­ 32-Bit/16-Bit, 533-MHz (data rate) Bus ­ 512M-Byte Total Addressable External Memory Space · EDMA3 Controller (64 Independent Channels) · 32-/16-Bit Host-Port Interface (HPI) · 32-Bit 33-/66-MHz, 3. 3-V Peripheral Component Interconnect (PCI) Master/Slave Interface Conforms to PCI Local Bus Specification (v2. 3) · One Inter-Integrated Circuit (I2C) Bus · Two McBSPs · 10/100/1000 Mb/s Ethernet MAC (EMAC) ­ IEEE 802. 3 Compliant ­ Supports Multiple Media Independent Interfaces (MII, GMII, RMII, and RGMII) ­ 8 Independent Transmit (TX) and 8 Independent Receive (RX) Channels · Two 64-Bit General-Purpose Timers, Configurable as Four 32-Bit Timers · UTOPIA ­ UTOPIA Level 2 Slave ATM Controller ­ 8-Bit Transmit and Receive Operations up to 50 MHz per Direction ­ User-Defined Cell Format up to 64 Bytes · 16 General-Purpose I/O (GPIO) Pins · System PLL and PLL Controller · Secondary PLL and PLL Controller, Dedicated to EMAC and DDR2 Memory Controller · Advanced Event Triggering (AET) Compatible · Trace-Enabled Device · IEEE-1149. 1 (JTAGTM) Boundary-Scan-Compatible · 697-Pin Ball Grid Array (BGA) Package (ZTZ or GTZ Suffix), 0. 8-mm Ball Pitch · 0. 09-mm/7-Level Cu Metal Process (CMOS) 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. Copyright © 2005­2010, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. TMS320C6455 SPRS276J ­ MAY 2005 ­ REVISED SEPTEMBER 2010 www. ti. com · 3. 3-/1. 8-/1. 5-/1. 25-/1. 2-V I/Os, 1. 25-/1. 2-V Internal 1. 1 ZTZ/GTZ BGA Package (Bottom View) Figure 1-1 shows the TMS320C6455 device 697-pin ball grid array package (bottom view). ZTZ/GTZ 697-PIN BALL GRID ARRAY (BGA) PACKAGE ( BOTTOM VIEW ) AJ AH AF AD AB Y V U T R P M K J H G F D C B A 1 2 3 4 5 6 7 8 9 11 13 15 17 19 21 23 25 27 29 10 12 14 16 18 20 22 24 26 28 E N L AG AE AC AA W NOTE: The ZTZ mechanical package designator represents the version of the GTZ package with lead-free balls. [. . . ] · RSV13 - connect this pin to ground (VSS) via a 200- resistor. · RSV14 - connect this pin to the 1. 8-V I/O supply (DVDD18) via a 200- resistor. Similarly, when the DDR2 Memory Controller is not used, the VREFSSTL, RSV11, and RSV12 pins can be connected directly to ground (VSS) to save power. However, this will prevent boundary-scan from functioning on the DDR2 Memory Controller pins. To preserve boundary-scan functionality on the DDR2 Memory Controller pins, VREFSSTL, RSV11, and RSV12 should be connected as follows: · VREFSSTL - connect to a voltage of DVDD18/2. The DVDD18/2 voltage can be generated directly from the DVDD18 supply using two 1-k resistors to form a resistor divider circuit. · RSV11 - connect this pin to ground (VSS) via a 200- resistor. · RSV12 - connect this pin to the 1. 8-V I/O supply (DVDD18) via a 200- resistor. Copyright © 2005­2010, Texas Instruments Incorporated C64x+ Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320C6455 105 TMS320C6455 SPRS276J ­ MAY 2005 ­ REVISED SEPTEMBER 2010 www. ti. com 7. 4 Enhanced Direct Memory Access (EDMA3) Controller The primary purpose of the EDMA3 is to service user-programmed data transfers between two memory-mapped slave endpoints on the device. The EDMA3 services software-driven paging transfers (e. g. , data movement between external memory and internal memory), performs sorting or subframe extraction of various data structures, services event driven peripherals such as a McBSP or the UTOPIA port , and offloads data transfers from the device CPU. The EDMA3 includes the following features: · Fully orthogonal transfer description ­ 3 transfer dimensions: array (multiple bytes), frame (multiple arrays), and block (multiple frames) ­ Single event can trigger transfer of array, frame, or entire block ­ Independent indexes on source and destination · Flexible transfer definition: ­ Increment or FIFO transfer addressing modes ­ Linking mechanism allows for ping-pong buffering, circular buffering, and repetitive/continuous transfers, all with no CPU intervention ­ Chaining allows multiple transfers to execute with one event · 256 PaRAM entries ­ Used to define transfer context for channels ­ Each PaRAM entry can be used as a DMA entry, QDMA entry, or link entry · 64 DMA channels ­ Manually triggered (CPU writes to channel controller register), external event triggered, and chain triggered (completion of one transfer triggers another) · 4 Quick DMA (QDMA) channels ­ Used for software-driven transfers ­ Triggered upon writing to a single PaRAM set entry · 4 transfer controllers/event queues with programmable system-level priority · Interrupt generation for transfer completion and error conditions · Memory protection support ­ Active memory protection for accesses to PaRAM and registers · Debug visibility ­ Queue watermarking/threshold allows detection of maximum usage of event queues ­ Error and status recording to facilitate debug Each of the transfer controllers has a direct connection to the switched central resource (SCR). NOTE Although the transfer controllers are directly connected to the SCR, they can only access certain device resources. lists the device resources that can be accessed by each of the transfer controllers. 106 C64x+ Peripheral Information and Electrical Specifications Copyright © 2005­2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320C6455 TMS320C6455 www. ti. com SPRS276J ­ MAY 2005 ­ REVISED SEPTEMBER 2010 7. 4. 1 EDMA3 Device-Specific Information The EDMA supports two addressing modes: constant addressing and increment addressing mode. Constant addressing mode is applicable to a very limited set of use cases; for most applications increment mode can be used. On the C6455 DSP, the EDMA can use constant addressing mode only with the Enhanced Viterbi-Decoder Coprocessor (VCP2) and the Enhanced Turbo Decoder Coprocessor (TCP2). Constant addressing mode is not supported by any other peripheral or internal memory in the C6455 DSP. Note that increment mode is supported by all C6455 peripherals, including VCP2 and TCP2. For more information on these two addressing modes, see the TMS320C645x DSP Enhanced DMA (EDMA3) Controller User's Guide (literature number SPRU966) . A DSP interrupt must be generated at the end of an HPI or PCI boot operation to begin execution of the loaded application. Since the DSP interrupt generated by the HPI and PCI is mapped to the EDMA event DSP_EVT (DMA channel 0), it will get recorded in bit 0 of the EDMA Event Register (ER). This event must be cleared by software before triggering transfers on DMA channel 0. The EDMA3 on the C6455 DSP supports active memory protection, but it does not support proxied memory protection. 7. 4. 2 EDMA3 Channel Synchronization Events The EDMA3 supports up to 64 DMA channels that can be used to service system peripherals and to move data between system memories. DMA channels can be triggered by synchronization events generated by system peripherals. [. . . ] In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. [. . . ]