User manual TEXAS INSTRUMENTS TMS320C6454 DATASHEET 09-2010

[. . . ] TMS320C6454 www. ti. com SPRS311F ­ APRIL 2006 ­ REVISED SEPTEMBER 2010 TMS320C6454 Fixed-Point Digital Signal Processor Check for Samples: TMS320C6454 1 Features 12 · High-Performance Fixed-Point DSP (C6454) ­ 1. 39-, 1. 17-, and 1-ns Instruction Cycle Time ­ 720-MHz, 850-MHz, and 1-GHz Clock Rate ­ Eight 32-Bit Instructions/Cycle ­ 8000 MIPS/MMACS (16-Bits) ­ Commercial Temperature [0°C to 90°C] ­ Extended Temperature [-40°C to 105°C] · TMS320C64x+TM DSP Core ­ Dedicated SPLOOP Instruction ­ Compact Instructions (16-Bit) ­ Instruction Set Enhancements ­ Exception Handling · TMS320C64x+ Megamodule L1/L2 Memory Architecture: ­ 256K-Bit (32K-Byte) L1P Program Cache [Direct Mapped] ­ 256K-Bit (32K-Byte) L1D Data Cache [2-Way Set-Associative] ­ 8M-Bit (1048K-Byte) L2 Unified Mapped RAM/Cache [Flexible Allocation] ­ 256K-Bit (32K-Byte) L2 ROM ­ Time Stamp Counter · Endianess: Little Endian, Big Endian · 64-Bit External Memory Interface (EMIFA) ­ Glueless Interface to Asynchronous Memories (SRAM, Flash, and EEPROM) and Synchronous Memories (SBSRAM, ZBT SRAM) ­ Supports Interface to Standard Sync Devices and Custom Logic (FPGA, CPLD, ASICs, etc. ) ­ 32M-Byte Total Addressable External Memory Space · DDR2 Memory Controller ­ Interfaces to DDR2-533 SDRAM ­ 32-Bit/16-Bit, 533-MHz (data rate) Bus ­ 512M-Byte Total Addressable External Memory Space · EDMA3 Controller (64 Independent Channels) · 32-/16-Bit Host-Port Interface (HPI) · 32-Bit 33-/66-MHz, 3. 3-V Peripheral Component Interconnect (PCI) Master/Slave Interface Conforms to PCI Local Bus Specification (v2. 3) · One Inter-Integrated Circuit (I2C) Bus · Two McBSPs · 10/100/1000 Mb/s Ethernet MAC (EMAC) ­ IEEE 802. 3 Compliant ­ Supports Multiple Media Independent Interfaces (MII, GMII, RMII, and RGMII) ­ 8 Independent Transmit (TX) and 8 Independent Receive (RX) Channels · Two 64-Bit General-Purpose Timers, Configurable as Four 32-Bit Timers · 16 General-Purpose I/O (GPIO) Pins · System PLL and PLL Controller · Secondary PLL and PLL Controller, Dedicated to EMAC and DDR2 Memory Controller · Advanced Event Triggering (AET) Compatible · Trace-Enabled Device · IEEE-1149. 1 (JTAGTM) Boundary-Scan-Compatible · 697-Pin Ball Grid Array (BGA) Package (ZTZ or GTZ Suffix), 0. 8-mm Ball Pitch · 0. 09-mm/7-Level Cu Metal Process (CMOS) · 3. 3-/1. 8-/1. 5-V I/Os, 1. 25-/1. 2-V Internal · Pin-Compatible with the TMS320C6455 Fixed-Point Digital Signal Processor 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. Copyright © 2006­2010, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. TMS320C6454 SPRS311F ­ APRIL 2006 ­ REVISED SEPTEMBER 2010 www. ti. com 1. 1 ZTZ/GTZ BGA Package (Bottom View) Figure 1-1 shows the TMS320C6454 device 697-pin ball grid array package (bottom view). ZTZ/GTZ 697-PIN BALL GRID ARRAY (BGA) PACKAGE ( BOTTOM VIEW ) AJ AH AF AD AB Y V U T R P M K J H G F D C B A 1 2 3 4 5 6 7 8 9 11 13 15 17 19 21 23 25 27 29 10 12 14 16 18 20 22 24 26 28 E N L AG AE AC AA W NOTE: The ZTZ mechanical package designator represents the version of the GTZ package with lead-free balls. [. . . ] This event must be cleared by software before triggering transfers on DMA channel 0. C64x+ Peripheral Information and Electrical Specifications Copyright © 2006­2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320C6454 TMS320C6454 www. ti. com SPRS311F ­ APRIL 2006 ­ REVISED SEPTEMBER 2010 Table 7-3. C6454 EDMA3 Channel Synchronization Events (continued) EDMA CHANNEL 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 BINARY 011 0000 011 0001 011 0010 011 0011 011 0100 011 0101 011 0110 011 0111 011 1000 011 1001 011 1010 011 1011 011 1100 011 1101 011 1110 011 1111 EVENT NAME GPINT0 GPINT1 GPINT2 GPINT3 GPINT4 GPINT5 GPINT6 GPINT7 GPINT8 GPINT9 GPINT10 GPINT11 GPINT12 GPINT13 GPINT14 GPINT15 GPIO event 0 GPIO event 1 GPIO event 2 GPIO event 3 GPIO event 4 GPIO event 5 GPIO event 6 GPIO event 7 GPIO event 8 GPIO event 9 GPIO event 10 GPIO event 11 GPIO event 12 GPIO event 13 GPIO event 14 GPIO event 15 EVENT DESCRIPTION 7. 4. 3 EDMA3 Peripheral Register Descriptions Table 7-4. EDMA3 Channel Controller Registers HEX ADDRESS RANGE 02A0 0000 02A0 0004 02A0 0008 - 02A0 00FC 02A0 0100 02A0 0104 02A0 0108 02A0 010C 02A0 0110 02A0 0114 02A0 0118 02A0 011C 02A0 0120 02A0 0124 02A0 0128 02A0 012C 02A0 0130 02A0 0134 02A0 0138 02A0 013C 02A0 0140 02A0 0144 02A0 0148 02A0 014C 02A0 0150 02A0 0154 ACRONYM PID CCCFG DCHMAP0 DCHMAP1 DCHMAP2 DCHMAP3 DCHMAP4 DCHMAP5 DCHMAP6 DCHMAP7 DCHMAP8 DCHMAP9 DCHMAP10 DCHMAP11 DCHMAP12 DCHMAP13 DCHMAP14 DCHMAP15 DCHMAP16 DCHMAP17 DCHMAP18 DCHMAP19 DCHMAP20 DCHMAP21 Peripheral ID Register EDMA3CC Configuration Register Reserved DMA Channel 0 Mapping Register DMA Channel 1 Mapping Register DMA Channel 2 Mapping Register DMA Channel 3 Mapping Register DMA Channel 4 Mapping Register DMA Channel 5 Mapping Register DMA Channel 6 Mapping Register DMA Channel 7 Mapping Register DMA Channel 8 Mapping Register DMA Channel 9 Mapping Register DMA Channel 10 Mapping Register DMA Channel 11 Mapping Register DMA Channel 12 Mapping Register DMA Channel 13 Mapping Register DMA Channel 14 Mapping Register DMA Channel 15 Mapping Register DMA Channel 16 Mapping Register DMA Channel 17 Mapping Register DMA Channel 18 Mapping Register DMA Channel 19 Mapping Register DMA Channel 20 Mapping Register DMA Channel 21 Mapping Register REGISTER NAME Copyright © 2006­2010, Texas Instruments Incorporated C64x+ Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320C6454 103 TMS320C6454 SPRS311F ­ APRIL 2006 ­ REVISED SEPTEMBER 2010 www. ti. com Table 7-4. EDMA3 Channel Controller Registers (continued) HEX ADDRESS RANGE 02A0 0158 02A0 015C 02A0 0160 02A0 0164 02A0 0168 02A0 016C 02A0 0170 02A0 0174 02A0 0178 02A0 017C 02A0 0180 02A0 0184 02A0 0188 02A0 018C 02A0 0190 02A0 0194 02A0 0198 02A0 019C 02A0 01A0 02A0 01A4 02A0 01A8 02A0 01AC 02A0 01B0 02A0 01B4 02A0 01B8 02A0 01BC 02A0 01C0 02A0 01C4 02A0 01C8 02A0 01CC 02A0 01D0 02A0 01D4 02A0 01D8 02A0 01DC 02A0 01E0 02A0 01E4 02A0 01E8 02A0 01EC 02A0 01F0 02A0 01F4 02A0 01F8 02A0 01FC 02A0 0200 02A0 0204 02A0 0208 02A0 020C 02A0 0210 - 02A0 021C ACRONYM DCHMAP22 DCHMAP23 DCHMAP24 DCHMAP25 DCHMAP26 DCHMAP27 DCHMAP28 DCHMAP29 DCHMAP30 DCHMAP31 DCHMAP32 DCHMAP33 DCHMAP34 DCHMAP35 DCHMAP36 DCHMAP37 DCHMAP38 DCHMAP39 DCHMAP40 DCHMAP41 DCHMAP42 DCHMAP43 DCHMAP44 DCHMAP45 DCHMAP46 DCHMAP47 DCHMAP48 DCHMAP49 DCHMAP50 DCHMAP51 DCHMAP52 DCHMAP53 DCHMAP54 DCHMAP55 DCHMAP56 DCHMAP57 DCHMAP58 DCHMAP59 DCHMAP60 DCHMAP61 DCHMAP62 DCHMAP63 QCHMAP0 QCHMAP1 QCHMAP2 QCHMAP3 REGISTER NAME DMA Channel 22 Mapping Register DMA Channel 23 Mapping Register DMA Channel 24 Mapping Register DMA Channel 25 Mapping Register DMA Channel 26 Mapping Register DMA Channel 27 Mapping Register DMA Channel 28 Mapping Register DMA Channel 29 Mapping Register DMA Channel 30 Mapping Register DMA Channel 31 Mapping Register DMA Channel 32 Mapping Register DMA Channel 33 Mapping Register DMA Channel 34 Mapping Register DMA Channel 35 Mapping Register DMA Channel 36 Mapping Register DMA Channel 37 Mapping Register DMA Channel 38 Mapping Register DMA Channel 39 Mapping Register DMA Channel 40 Mapping Register DMA Channel 41 Mapping Register DMA Channel 42 Mapping Register DMA Channel 43 Mapping Register DMA Channel 44 Mapping Register DMA Channel 45 Mapping Register DMA Channel 46 Mapping Register DMA Channel 47 Mapping Register DMA Channel 48 Mapping Register DMA Channel 49 Mapping Register DMA Channel 50 Mapping Register DMA Channel 51 Mapping Register DMA Channel 52 Mapping Register DMA Channel 53 Mapping Register DMA Channel 54 Mapping Register DMA Channel 55 Mapping Register DMA Channel 56 Mapping Register DMA Channel 57 Mapping Register DMA Channel 58 Mapping Register DMA Channel 59 Mapping Register DMA Channel 60 Mapping Register DMA Channel 61 Mapping Register DMA Channel 62 Mapping Register DMA Channel 63 Mapping Register QDMA Channel 0 Mapping Register QDMA Channel 1 Mapping Register QDMA Channel 2 Mapping Register QDMA Channel 3 Mapping Register Reserved 104 C64x+ Peripheral Information and Electrical Specifications Copyright © 2006­2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320C6454 TMS320C6454 www. ti. com SPRS311F ­ APRIL 2006 ­ REVISED SEPTEMBER 2010 Table 7-4. EDMA3 Channel Controller Registers (continued) HEX ADDRESS RANGE 02A0 0220 - 02A0 023C 02A0 0240 02A0 0244 02A0 0248 02A0 024C 02A0 0250 02A0 0254 02A0 0258 02A0 025C 02A0 0260 02A0 0264 - 02A0 0280 02A0 0284 02A0 0288 - 02A0 02FC 02A0 0300 02A0 0304 02A0 0308 02A0 030C 02A0 0310 02A0 0314 02A0 0318 02A0 031C 02A0 0320 02A0 0324 - 02A0 033C 02A0 0340 02A0 0344 02A0 0348 02A0 034C 02A0 0350 02A0 0354 02A0 0358 02A0 035C 02A0 0360 02A0 0364 02A0 0368 02A0 036C 02A0 0370 02A0 0374 02A0 0378 02A0 037C 02A0 0380 02A0 0384 02A0 0388 02A0 038C 02A0 0390 - 02A0 039C 02A0 0400 02A0 0404 02A0 0408 ACRONYM DMAQNUM0 DMAQNUM1 DMAQNUM2 DMAQNUM3 DMAQNUM4 DMAQNUM5 DMAQNUM6 DMAQNUM7 QDMAQNUM QUEPRI EMR EMRH EMCR EMCRH QEMR QEMCR CCERR CCERRCLR EEVAL DRAE0 DRAEH0 DRAE1 DRAEH1 DRAE2 DRAEH2 DRAE3 DRAEH3 DRAE4 DRAEH4 DRAE5 DRAEH5 DRAE6 DRAEH6 DRAE7 DRAEH7 QRAE0 QRAE1 QRAE2 QRAE3 Q0E0 Q0E1 Q0E2 Reserved DMA Queue Number Register 0 DMA Queue Number Register 1 DMA Queue Number Register 2 DMA Queue Number Register 3 DMA Queue Number Register 4 DMA Queue Number Register 5 DMA Queue Number Register 6 DMA Queue Number Register 7 QDMA Queue Number Register Reserved Queue Priority Register Reserved Event Missed Register Event MissedRegister High Event Missed Clear Register Event Missed Clear Register High QDMA Event Missed Register QDMA Event Missed Clear Register EDMA3CC Error Register EDMA3CC Error Clear Register Error Evaluate Register Reserved DMA Region Access Enable Register for Region 0 DMA Region Access Enable Register High for Region 0 DMA Region Access Enable Register for Region 1 DMA Region Access Enable Register High for Region 1 DMA Region Access Enable Register for Region 2 DMA Region Access Enable Register High for Region 2 DMA Region Access Enable Register for Region 3 DMA Region Access Enable Register High for Region 3 DMA Region Access Enable Register for Region 4 DMA Region Access Enable Register High for Region 4 DMA Region Access Enable Register for Region 5 DMA Region Access Enable Register High for Region 5 DMA Region Access Enable Register for Region 6 DMA Region Access Enable Register High for Region 6 DMA Region Access Enable Register for Region 7 DMA Region Access Enable Register High for Region 7 QDMA Region Access Enable Register for Region 0 QDMA Region Access Enable Register for Region 1 QDMA Region Access Enable Register for Region 2 QDMA Region Access Enable Register for Region 3 Reserved Event Queue 0 Entry Register 0 Event Queue 0 Entry Register 1 Event Queue 0 Entry Register 2 REGISTER NAME Copyright © 2006­2010, Texas Instruments Incorporated C64x+ Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320C6454 105 TMS320C6454 SPRS311F ­ APRIL 2006 ­ REVISED SEPTEMBER 2010 www. ti. com Table 7-4. EDMA3 Channel Controller Registers (continued) HEX ADDRESS RANGE 02A0 040C 02A0 0410 02A0 0414 02A0 0418 02A0 041C 02A0 0420 02A0 0424 02A0 0428 02A0 042C 02A0 0430 02A0 0434 02A0 0438 02A0 043C 02A0 0440 02A0 0444 02A0 0448 02A0 044C 02A0 0450 02A0 0454 02A0 0458 02A0 045C 02A0 0460 02A0 0464 02A0 0468 02A0 046C 02A0 0470 02A0 0474 02A0 0478 02A0 047C 02A0 0480 02A0 0484 02A0 0488 02A0 048C 02A0 0490 02A0 0494 02A0 0498 02A0 049C 02A0 04A0 02A0 04A4 02A0 04A8 02A0 04AC 02A0 04B0 02A0 04B4 02A0 04B8 02A0 04BC 02A0 04C0 02A0 04C4 ACRONYM Q0E3 Q0E4 Q0E5 Q0E6 Q0E7 Q0E8 Q0E9 Q0E10 Q0E11 Q0E12 Q0E13 Q0E14 Q0E15 Q1E0 Q1E1 Q1E2 Q1E3 Q1E4 Q1E5 Q1E6 Q1E7 Q1E8 Q1E9 Q1E10 Q1E11 Q1E12 Q1E13 Q1E14 Q1E15 Q2E0 Q2E1 Q2E2 Q2E3 Q2E4 Q2E5 Q2E6 Q2E7 Q2E8 Q2E9 Q2E10 Q2E11 Q2E12 Q2E13 Q2E14 Q2E15 Q3E0 Q3E1 REGISTER NAME Event Queue 0 Entry Register 3 Event Queue 0 Entry Register 4 Event Queue 0 Entry Register 5 Event Queue 0 Entry Register 6 Event Queue 0 Entry Register 7 Event Queue 0 Entry Register 8 Event Queue 0 Entry Register 9 Event Queue 0 Entry Register 10 Event Queue 0 Entry Register 11 Event Queue 0 Entry Register 12 Event Queue 0 Entry Register 13 Event Queue 0 Entry Register 14 Event Queue 0 Entry Register 15 Event Queue 1 Entry Register 0 Event Queue 1 Entry Register 1 Event Queue 1 Entry Register 2 Event Queue 1 Entry Register 3 Event Queue 1 Entry Register 4 Event Queue 1 Entry Register 5 Event Queue 1 Entry Register 6 Event Queue 1 Entry Register 7 Event Queue 1 Entry Register 8 Event Queue 1 Entry Register 9 Event Queue 1 Entry Register 10 Event Queue 1 Entry Register 11 Event Queue 1 Entry Register 12 Event Queue 1 Entry Register 13 Event Queue 1 Entry Register 14 Event Queue 1 Entry Register 15 Event Queue 2 Entry Register 0 Event Queue 2 Entry Register 1 Event Queue 2 Entry Register 2 Event Queue 2 Entry Register 3 Event Queue 2 Entry Register 4 Event Queue 2 Entry Register 5 Event Queue 2 Entry Register 6 Event Queue 2 Entry Register 7 Event Queue 2 Entry Register 8 Event Queue 2 Entry Register 9 Event Queue 2 Entry Register 10 Event Queue 2 Entry Register 11 Event Queue 2 Entry Register 12 Event Queue 2 Entry Register 13 Event Queue 2 Entry Register 14 Event Queue 2 Entry Register 15 Event Queue 3 Entry Register 0 Event Queue 3 Entry Register 1 106 C64x+ Peripheral Information and Electrical Specifications Copyright © 2006­2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320C6454 TMS320C6454 www. ti. com SPRS311F ­ APRIL 2006 ­ REVISED SEPTEMBER 2010 Table 7-4. EDMA3 Channel Controller Registers (continued) HEX ADDRESS RANGE 02A0 04C8 02A0 04CC 02A0 04D0 02A0 04D4 02A0 04D8 02A0 04DC 02A0 04E0 02A0 04E4 02A0 04E8 02A0 04EC 02A0 04F0 02A0 04F4 02A0 04F8 02A0 04FC 02A0 0500 - 02A0 051C 02A0 0520 - 02A0 05FC 02A0 0600 02A0 0604 02A0 0608 02A0 060C 02A0 0610 - 02A0 061C 02A0 0620 02A0 0624 - 02A0 063C 02A0 0640 02A0 0644 - 02A0 06FC 02A0 0700 - 02A0 07FC 02A0 0800 02A0 0804 02A0 0808 02A0 080C 02A0 0810 02A0 0814 02A0 0818 02A0 081C 02A0 0820 02A0 0824 02A0 0828 02A0 082C - 02A0 0FFC 02A0 1000 02A0 1004 02A0 1008 02A0 100C 02A0 1010 02A0 1014 02A0 1018 02A0 101C 02A0 1020 ACRONYM Q3E2 Q3E3 Q3E4 Q3E5 Q3E6 Q3E7 Q3E8 Q3E9 Q3E10 Q3E11 Q3E12 Q3E13 Q3E14 Q3E15 QSTAT0 QSTAT1 QSTAT2 QSTAT3 QWMTHRA CCSTAT MPFAR MPFSR MPFCR MPPA0 MPPA1 MPPA2 MPPA3 MPPA4 MPPA5 MPPA6 MPPA7 ER ERH ECR ECRH ESR ESRH CER CERH EER REGISTER NAME Event Queue 3 Entry Register 2 Event Queue 3 Entry Register 3 Event Queue 3 Entry Register 4 Event Queue 3 Entry Register 5 Event Queue 3 Entry Register 6 Event Queue 3 Entry Register 7 Event Queue 3 Entry Register 8 Event Queue 3 Entry Register 9 Event Queue 3 Entry Register 10 Event Queue 3 Entry Register 11 Event Queue 3 Entry Register 12 Event Queue 3 Entry Register 13 Event Queue 3 Entry Register 14 Event Queue 3 Entry Register 15 Reserved Reserved Queue Status Register 0 Queue Status Register 1 Queue Status Register 2 Queue Status Register 3 Reserved Queue Watermark Threshold A Register Reserved EDMA3CC Status Register Reserved Reserved Memory Protection Fault Address Register Memory Protection Fault Status Register Memory Protection Fault Command Register Memory Protection Page Attribute Register 0 Memory Protection Page Attribute Register 1 Memory Protection Page Attribute Register 2 Memory Protection Page Attribute Register 3 Memory Protection Page Attribute Register 4 Memory Protection Page Attribute Register 5 Memory Protection Page Attribute Register 6 Memory Protection Page Attribute Register 7 Reserved Event Register Event Register High Event Clear Register Event Clear Register High Event Set Register Event Set Register High Chained Event Register Chained Event Register High Event Enable Register Copyright © 2006­2010, Texas Instruments Incorporated C64x+ Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320C6454 107 TMS320C6454 SPRS311F ­ APRIL 2006 ­ REVISED SEPTEMBER 2010 www. ti. com Table 7-4. EDMA3 Channel Controller Registers (continued) HEX ADDRESS RANGE 02A0 1024 02A0 1028 02A0 102C 02A0 1030 02A0 1034 02A0 1038 02A0 103C 02A0 1040 02A0 1044 02A0 1048 - 02A0 104C 02A0 1050 02A0 1054 02A0 1058 02A0 105C 02A0 1060 02A0 1064 02A0 1068 02A0 106C 02A0 1070 02A0 1074 02A0 1078 02A0 107C 02A0 1080 02A0 1084 02A0 1088 02A0 108C 02A0 1090 02A0 1094 02A0 1098 - 02A0 1FFF 02A0 2000 02A0 2004 02A0 2008 02A0 200C 02A0 2010 02A0 2014 02A0 2018 02A0 201C 02A0 2020 02A0 2024 02A0 2028 02A0 202C 02A0 2030 02A0 2034 02A0 2038 02A0 203C 02A0 2040 ACRONYM EERH EECR EECRH EESR EESRH SER SERH SECR SECRH IER IERH IECR IECRH IESR IESRH IPR IPRH ICR ICRH IEVAL QER QEER QEECR QEESR QSER QSECR ER ERH ECR ECRH ESR ESRH CER CERH EER EERH EECR EECRH EESR EESRH SER SERH SECR Event Enable Register High Event Enable Clear Register Event Enable Clear Register High Event Enable Set Register Event Enable Set Register High Secondary Event Register Secondary Event Register High Secondary Event Clear Register Secondary Event Clear Register High Reserved Interrupt Enable Register Interrupt Enable High Register Interrupt Enable Clear Register Interrupt Enable Clear High Register Interrupt Enable Set Register Interrupt Enable Set High Register Interrupt Pending Register Interrupt Pending High Register Interrupt Clear Register Interrupt Clear High Register Interrupt Evaluate Register Reserved QDMA Event Register QDMA Event Enable Register QDMA Event Enable Clear Register QDMA Event Enable Set Register QDMA Secondary Event Register QDMA Secondary Event Clear Register Reserved Event Register Event Register High Event Clear Register Event Clear Register High Event Set Register Event Set Register High Chained Event Register Chained Event Register Hig Event Enable Register Event Enable Register High Event Enable Clear Register Event Enable Clear Register High Event Enable Set Register Event Enable Set Register High Secondary Event Register Secondary Event Register High Secondary Event Clear Register REGISTER NAME Shadow Region 0 Channel Registers 108 C64x+ Peripheral Information and Electrical Specifications Copyright © 2006­2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320C6454 TMS320C6454 www. ti. com SPRS311F ­ APRIL 2006 ­ REVISED SEPTEMBER 2010 Table 7-4. EDMA3 Channel Controller Registers (continued) HEX ADDRESS RANGE 02A0 2044 02A0 2048 - 02A0 204C 02A0 2050 02A0 2054 02A0 2058 02A0 205C 02A0 2060 02A0 2064 02A0 2068 02A0 206C 02A0 2070 02A0 2074 02A0 2078 02A0 207C 02A0 2080 02A0 2084 02A0 2088 02A0 208C 02A0 2090 02A0 2094 02A0 2098 - 02A0 23FF 02A0 2400 - 02A0 2497 02A0 2498 - 02A0 25FF 02A0 2600 - 02A0 2697 02A0 2698 - 02A0 27FF 02A0 2800 - 02A0 2897 02A0 2898 - 02A0 29FF 02A0 2A00 - 02A0 2A97 02A0 2A98 - 02A0 2BFF 02A0 2C00 - 02A0 2C97 02A0 2C98 - 02A0 2DFF 02A0 2E00 - 02A0 2E97 02A0 2E98 - 02A0 2FFF ACRONYM SECRH IER IERH IECR IECRH IESR IESRH IPR IPRH ICR ICRH IEVAL QER QEER QEECR QEESR QSER QSECR Reserved Interrupt Enable Register Interrupt Enable Register High Interrupt Enable Clear Register Interrupt Enable Clear Register High Interrupt Enable Set Register Interrupt Enable Set Register High Interrupt Pending Register Interrupt Pending Register High Interrupt Clear Register Interrupt Clear Register High Interrupt Evaluate Register Reserved QDMA Event Register QDMA Event Enable Register QDMA Event Enable Clear Register QDMA Event Enable Set Register QDMA Secondary Event Register QDMA Secondary Event Clear Register Reserved Shadow Region 2 Channel Registers Reserved Shadow Region 3 Channel Registers Reserved Shadow Region 4 Channel Registers Reserved Shadow Region 5 Channel Registers Reserved Shadow Region 6 Channel Registers Reserved Shadow Region 7 Channel Registers Reserved REGISTER NAME Secondary Event Clear Register High Table 7-5. EDMA3 Parameter RAM (1) HEX ADDRESS RANGE 02A0 4000 - 02A0 401F 02A0 4020 - 02A0 403F 02A0 4040 - 02A0 405F 02A0 4060 - 02A0 407F 02A0 4080 - 02A0 409F 02A0 40A0 - 02A0 40BF 02A0 40C0 - 02A0 40DF 02A0 40E0 - 02A0 40FF 02A0 4100 - 02A0 411F (1) ACRONYM Parameter Set 0 Parameter Set 1 Parameter Set 2 Parameter Set 3 Parameter Set 4 Parameter Set 5 Parameter Set 6 Parameter Set 7 Parameter Set 8 REGISTER NAME The C6454 device has 256 EDMA3 parameter sets total. Each parameter set can be used as a DMA entry, a QDMA entry, or a link entry. C64x+ Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320C6454 109 Copyright © 2006­2010, Texas Instruments Incorporated TMS320C6454 SPRS311F ­ APRIL 2006 ­ REVISED SEPTEMBER 2010 www. ti. com Table 7-5. EDMA3 Parameter RAM (continued) HEX ADDRESS RANGE 02A0 4120 - 02A0 413F . . . 02A0 5FC0 - 02A0 5FDF 02A0 5FE0 - 02A0 5FFF ACRONYM Parameter Set 9 . . . EDMA3 Transfer Controller 0 Registers HEX ADDRESS RANGE 02A2 0000 02A2 0004 02A2 0008 - 02A2 00FC 02A2 0100 02A2 0104 - 02A2 011C 02A2 0120 02A2 0124 02A2 0128 02A2 012C 02A2 0130 02A2 0134 - 02A2 013C 02A2 0140 02A2 0144 - 02A2 023C 02A2 0240 02A2 0244 02A2 0248 02A2 024C 02A2 0250 02A2 0254 02A2 0258 02A2 025C 02A2 0260 02A2 0264 - 02A2 027C 02A2 0280 02A2 0284 02A2 0288 02A2 028C - 02A2 02FC 02A2 0300 02A2 0304 02A2 0308 02A2 030C 02A2 0310 02A2 0314 02A2 0318 - 02A2 033C 02A2 0340 02A2 0344 110 ACRONYM PID TCCFG TCSTAT ERRSTAT ERREN ERRCLR ERRDET ERRCMD RDRATE SAOPT SASRC SACNT SADST SABIDX SAMPPRXY SACNTRLD SASRCBREF SADSTBREF DFCNTRLD DFSRCBREF DFDSTBREF DFOPT0 DFSRC0 DFCNT0 DFDST0 DFBIDX0 DFMPPRXY0 DFOPT1 DFSRC1 REGISTER NAME Peripheral Identification Register EDMA3TC Configuration Register Reserved EDMA3TC Channel Status Register Reserved Error Register Error Enable Register Error Clear Register Error Details Register Error Interrupt Command Register Reserved Read Rate Register Reserved Source Active Options Register Source Active Source Address Register Source Active Count Register Source Active Destination Address Register Source Active Source B-Index Register Source Active Memory Protection Proxy Register Source Active Count Reload Register Source Active Source Address B-Reference Register Source Active Destination Address B-Reference Register Reserved Destination FIFO Set Count Reload Destination FIFO Set Destination Address B Reference Register Destination FIFO Set Destination Address B Reference Register Reserved Destination FIFO Options Register 0 Destination FIFO Source Address Register 0 Destination FIFO Count Register 0 Destination FIFO Destination Address Register 0 Destination FIFO BIDX Register 0 Destination FIFO Memory Protection Proxy Register 0 Reserved Destination FIFO Options Register 1 Destination FIFO Source Address Register 1 C64x+ Peripheral Information and Electrical Specifications Copyright © 2006­2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320C6454 TMS320C6454 www. ti. com SPRS311F ­ APRIL 2006 ­ REVISED SEPTEMBER 2010 Table 7-6. EDMA3 Transfer Controller 0 Registers (continued) HEX ADDRESS RANGE 02A2 0348 02A2 034C 02A2 0350 02A2 0354 02A2 0358 - 02A2 037C 02A2 0380 02A2 0384 02A2 0388 02A2 038C 02A2 0390 02A2 0394 02A2 0398 - 02A2 03BC 02A2 03C0 02A2 03C4 02A2 03C8 02A2 03CC 02A2 03D0 02A2 03D4 02A2 03D8 - 02A2 7FFF ACRONYM DFCNT1 DFDST1 DFBIDX1 DFMPPRXY1 DFOPT2 DFSRC2 DFCNT2 DFDST2 DFBIDX2 DFMPPRXY2 DFOPT3 DFSRC3 DFCNT3 DFDST3 DFBIDX3 DFMPPRXY3 REGISTER NAME Destination FIFO Count Register 1 Destination FIFO Destination Address Register 1 Destination FIFO BIDX Register 1 Destination FIFO Memory Protection Proxy Register 1 Reserved Destination FIFO Options Register 2 Destination FIFO Source Address Register 2 Destination FIFO Count Register 2 Destination FIFO Destination Address Register 2 Destination FIFO BIDX Register 2 Destination FIFO Memory Protection Proxy Register 2 Reserved Destination FIFO Options Register 3 Destination FIFO Source Address Register 3 Destination FIFO Count Register 3 Destination FIFO Destination Address Register 3 Destination FIFO BIDX Register 3 Destination FIFO Memory Protection Proxy Register 3 Reserved Table 7-7. EDMA3 Transfer Controller 1 Registers HEX ADDRESS RANGE 02A2 8000 02A2 8004 02A2 8008 - 02A2 80FC 02A2 8100 02A2 8104 - 02A2 811C 02A2 8120 02A2 8124 02A2 8128 02A2 812C 02A2 8130 02A2 8134 - 02A2 813C 02A2 8140 02A2 8144 - 02A2 823C 02A2 8240 02A2 8244 02A2 8248 02A2 824C 02A2 8250 02A2 8254 02A2 8258 02A2 825C 02A2 8260 02A2 8264 - 02A2 827C 02A2 8280 02A2 8284 ACRONYM PID TCCFG TCSTAT ERRSTAT ERREN ERRCLR ERRDET ERRCMD RDRATE SAOPT SASRC SACNT SADST SABIDX SAMPPRXY SACNTRLD SASRCBREF SADSTBREF DFCNTRLD DFSRCBREF REGISTER NAME Peripheral Identification Register EDMA3TC Configuration Register Reserved EDMA3TC Channel Status Register Reserved Error Register Error Enable Register Error Clear Register Error Details Register Error Interrupt Command Register Reserved Read Rate Register Reserved Source Active Options Register Source Active Source Address Register Source Active Count Register Source Active Destination Address Register Source Active Source B-Index Register Source Active Memory Protection Proxy Register Source Active Count Reload Register Source Active Source Address B-Reference Register Source Active Destination Address B-Reference Register Reserved Destination FIFO Set Count Reload Destination FIFO Set Destination Address B Reference Register 111 Copyright © 2006­2010, Texas Instruments Incorporated C64x+ Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320C6454 TMS320C6454 SPRS311F ­ APRIL 2006 ­ REVISED SEPTEMBER 2010 www. ti. com Table 7-7. EDMA3 Transfer Controller 1 Registers (continued) HEX ADDRESS RANGE 02A2 8288 02A2 828C - 02A2 82FC 02A2 8300 02A2 8304 02A2 8308 02A2 830C 02A2 8310 02A2 8314 02A2 8318 - 02A2 833C 02A2 8340 02A2 8344 02A2 8348 02A2 834C 02A2 8350 02A2 8354 02A2 8358 - 02A2 837C 02A2 8380 02A2 8384 02A2 8388 02A2 838C 02A2 8390 02A2 8394 02A2 8398 - 02A2 83BC 02A2 83C0 02A2 83C4 02A2 83C8 02A2 83CC 02A2 83D0 02A2 83D4 02A2 83D8 - 02A2 FFFF ACRONYM DFDSTBREF DFOPT0 DFSRC0 DFCNT0 DFDST0 DFBIDX0 DFMPPRXY0 DFOPT1 DFSRC1 DFCNT1 DFDST1 DFBIDX1 DFMPPRXY1 DFOPT2 DFSRC2 DFCNT2 DFDST2 DFBIDX2 DFMPPRXY2 DFOPT3 DFSRC3 DFCNT3 DFDST3 DFBIDX3 DFMPPRXY3 REGISTER NAME Destination FIFO Set Destination Address B Reference Register Reserved Destination FIFO Options Register 0 Destination FIFO Source Address Register 0 Destination FIFO Count Register 0 Destination FIFO Destination Address Register 0 Destination FIFO BIDX Register 0 Destination FIFO Memory Protection Proxy Register 0 Reserved Destination FIFO Options Register 1 Destination FIFO Source Address Register 1 Destination FIFO Count Register 1 Destination FIFO Destination Address Register 1 Destination FIFO BIDX Register 1 Destination FIFO Memory Protection Proxy Register 1 Reserved Destination FIFO Options Register 2 Destination FIFO Source Address Register 2 Destination FIFO Count Register 2 Destination FIFO Destination Address Register 2 Destination FIFO BIDX Register 2 Destination FIFO Memory Protection Proxy Register 2 Reserved Destination FIFO Options Register 3 Destination FIFO Source Address Register 3 Destination FIFO Count Register 3 Destination FIFO Destination Address Register 3 Destination FIFO BIDX Register 3 Destination FIFO Memory Protection Proxy Register 3 Reserved Table 7-8. EDMA3 Transfer Controller 2 Registers HEX ADDRESS RANGE 02A3 0000 02A3 0004 02A3 0008 - 02A3 00FC 02A3 0100 02A3 0104 - 02A3 011C 02A3 0120 02A3 0124 02A3 0128 02A3 012C 02A3 0130 02A3 0134 - 02A3 013C 02A3 0140 02A3 0144 - 02A3 023C 02A3 0240 112 ACRONYM PID TCCFG TCSTAT ERRSTAT ERREN ERRCLR ERRDET ERRCMD RDRATE SAOPT REGISTER NAME Peripheral Identification Register EDMA3TC Configuration Register Reserved EDMA3TC Channel Status Register Reserved Error Register Error Enable Register Error Clear Register Error Details Register Error Interrupt Command Register Reserved Read Rate Register Reserved Source Active Options Register C64x+ Peripheral Information and Electrical Specifications Copyright © 2006­2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320C6454 TMS320C6454 www. ti. com SPRS311F ­ APRIL 2006 ­ REVISED SEPTEMBER 2010 Table 7-8. EDMA3 Transfer Controller 2 Registers (continued) HEX ADDRESS RANGE 02A3 0244 02A3 0248 02A3 024C 02A3 0250 02A3 0254 02A3 0258 02A3 025C 02A3 0260 02A3 0264 - 02A3 027C 02A3 0280 02A3 0284 02A3 0288 02A3 028C - 02A3 02FC 02A3 0300 02A3 0304 02A3 0308 02A3 030C 02A3 0310 02A3 0314 02A3 0318 - 02A3 033C 02A3 0340 02A3 0344 02A3 0348 02A3 034C 02A3 0350 02A3 0354 02A3 0358 - 02A3 037C 02A3 0380 02A3 0384 02A3 0388 02A3 038C 02A3 0390 02A3 0394 02A3 0398 - 02A3 03BC 02A3 03C0 02A3 03C4 02A3 03C8 02A3 03CC 02A3 03D0 02A3 03D4 02A3 03D8 - 02A3 7FFF ACRONYM SASRC SACNT SADST SABIDX SAMPPRXY SACNTRLD SASRCBREF SADSTBREF DFCNTRLD DFSRCBREF DFDSTBREF DFOPT0 DFSRC0 DFCNT0 DFDST0 DFBIDX0 DFMPPRXY0 DFOPT1 DFSRC1 DFCNT1 DFDST1 DFBIDX1 DFMPPRXY1 DFOPT2 DFSRC2 DFCNT2 DFDST2 DFBIDX2 DFMPPRXY2 DFOPT3 DFSRC3 DFCNT3 DFDST3 DFBIDX3 DFMPPRXY3 REGISTER NAME Source Active Source Address Register Source Active Count Register Source Active Destination Address Register Source Active Source B-Index Register Source Active Memory Protection Proxy Register Source Active Count Reload Register Source Active Source Address B-Reference Register Source Active Destination Address B-Reference Register Reserved Destination FIFO Set Count Reload Destination FIFO Set Destination Address B Reference Register Destination FIFO Set Destination Address B Reference Register Reserved Destination FIFO Options Register 0 Destination FIFO Source Address Register 0 Destination FIFO Count Register 0 Destination FIFO Destination Address Register 0 Destination FIFO BIDX Register 0 Destination FIFO Memory Protection Proxy Register 0 Reserved Destination FIFO Options Register 1 Destination FIFO Source Address Register 1 Destination FIFO Count Register 1 Destination FIFO Destination Address Register 1 Destination FIFO BIDX Register 1 Destination FIFO Memory Protection Proxy Register 1 Reserved Destination FIFO Options Register 2 Destination FIFO Source Address Register 2 Destination FIFO Count Register 2 Destination FIFO Destination Address Register 2 Destination FIFO BIDX Register 2 Destination FIFO Memory Protection Proxy Register 2 Reserved Destination FIFO Options Register 3 Destination FIFO Source Address Register 3 Destination FIFO Count Register 3 Destination FIFO Destination Address Register 3 Destination FIFO BIDX Register 3 Destination FIFO Memory Protection Proxy Register 3 Reserved Table 7-9. EDMA3 Transfer Controller 3 Registers HEX ADDRESS RANGE 02A3 8000 02A3 8004 02A3 8008 - 02A3 80FC Copyright © 2006­2010, Texas Instruments Incorporated ACRONYM PID TCCFG - REGISTER NAME Peripheral Identification Register EDMA3TC Configuration Register Reserved C64x+ Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320C6454 113 TMS320C6454 SPRS311F ­ APRIL 2006 ­ REVISED SEPTEMBER 2010 www. ti. com Table 7-9. [. . . ] In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. [. . . ]