User manual TEXAS INSTRUMENTS TLK6002 DATASHEET 08-2010

[. . . ] TLK6002 www. ti. com SLLSE34A ­ MAY 2010 ­ REVISED AUGUST 2010 Dual Channel 0. 47Gbps to 6. 25Gbps Multi-Rate Transceiver Check for Samples: TLK6002 1 Introduction 1. 1 1 Transceiver Features · Dual Power Supply: 1. 0V Core, and 1. 5V/1. 8V I/O Nominal Supply · Serial Side Three Tap Transmit De-emphasis and Receive Adaptive Equalization to Allow Extended Backplane Reach · Programmable Output Swing on Serial Output · Minimum Receiver Differential Input Thresholds of 100mVdfpp · Loss of Signal (LOS) detection (75 mVdfpp) · Interface to Back Plane, Copper Cables, or Optical Modules · Hot Plug Protection · JTAG; IEEE 1149. 1 /1149. 6 Test Interface · MDIO; IEEE 802. 3 Clause-22 Support · 65nm Advanced CMOS Technology · Industrial Ambient Operating Temp (­40°C to 85°C) at Full Rate · Device Package; 324 PBGA · Dual Channel 470Mbps to 6. 25Gbps Continuous/Multi-Rate Transceiver · Supports all CPRI and OBSAI Data Rates · Integrated Latency Measurement Function, Accuracy of ±814 ps · CPRI/OBSAI Automated Rate Sense (ARS) Function · Supports SERDES Operation, 8B/10B Data Modes (20-bit and 16-bit + Controls) · 20-bit HSTL Single-Ended Parallel Data Interface (Integrated Source and End Termination) · Shared or Independent Reference Clock per Channel · Latency/Depth Configurable Transmit and Receive FIFOs. · Loopback Capability (Serial and Parallel Side), OBSAI Compliant · Supports Serial Retime Operation · Supports PRBS (27­1), (223 ­ 1) and (231­1) and CRPAT Long/Short Generation and Verification 1. 2 · · · · · Applications WI Infrastructure CPRI and OBSAI Links Proprietary Links Backplane High Speed Point- to-Point Transmission Systems 1. 3 1. 3. 1 Overview Device Description The TLK6002 is a member of a portfolio of multi-gigabit transceivers, intended for use in ultra-high-speed bi-directional point-to-point data transmission systems. It is specifically intended for base station RRH (Remote Radio Head) application, but may also be used in other high speed applications. The TLK6002 supports a serial interface speed of 0. 470 Gbps to 6. 25 Gbps. [. . . ] ARS_TX_MDIO_GATE ­ ARS Transmit MDIO Gate ­ per channel Register bit 10. 11 ­ This bit is only relevant if TX_DATAPATH_OVERRIDE is asserted. When this bit is deasserted, upon successful ARS rate determination, the transmit datapath TX FIFO is automatically reset (centered) and continuity between the parallel input data and serial output is established without MDIO interaction. When this bit is asserted, the transmit datapath will not automatically switch over to serializing parallel input data at the time the ARS state machine successfully validates the incoming serial data rate (although the TX and RX FIFO are both automatically reset). This will give the opportunity for local MDIO firmware to interactively manage any additional device settings. Specifically this gives the device interfacing to TLK6002 the opportunity to read MDIO registers to determine the validated incoming serial rate, manage any other device or system settings required, and also manage TXCLK_A/B synchronicity to REFCLK at the proper data rate. After these steps are complete, the final step is to recenter the TX FIFO (by manually issuing a TX FIFO reset (TXFIFO_RESET register bit 4. 2). Transmit datapath reliable operation is fully restored after the TX FIFO reset MDIO write transaction is completed, and datapath continuity between parallel inputs and serial outputs is established. At the time when ARS rate determination is successful, both a TX and RX FIFO reset is automatically issued internal to TLK6002. Please note that if ARS_TX_MDIO_GATE is not asserted, there may be difficulty in effectively recentering the transmit fifo. This automatic recentering is triggered by the TXCLK_A/B and SERDES TX byte clock (multiplied up and divided down REFCLK_A/B) being asynchronous or having excessive phase drift. The TX FIFO is only effectively centered when the relationship between these two clocks has stabilized, at which point issuing a TX FIFO reset (manual or automatic through collision) will optimally center the TX FIFO. Note that careful external control of the TXCLK_A/B and REFCLK relationship (0 ppm and TXCLK_A/B at the right data rate) must be managed for the mode where ARS_TX_MDIO_GATE is deasserted to work reliably. If the clock relationship is still changing at the time of automatic recenter, the fifo may at some point in the future need to automatically recenter itself (via collision), at which time the transmit serial data will be briefly corrupted before resuming reliable operation. It is recommended that ARS_TX_MDIO_GATE is asserted unless careful system operation has been analyzed. In any ARS mode, note that the receive datapath software reset (not the same as RX FIFO reset) should not be issued as channel synchronization will be lost, and ARS would inappropriately begin searching for the incoming serial rate again (which is undesirable). 2. 22. 1 Receive Parallel Output Data During ARS Mode The parallel outputs are always driven during ARS mode. During ARS mode, it is anticipated that channel synchronization will typically remain lost during the rate determination process, and thus the parallel output data will typically behave predictably as indicated in the previous paragraph labeled Receive Datapath Error Condition Operation. 38 Description Submit Documentation Feedback Product Folder Link(s): TLK6002 Copyright © 2010, Texas Instruments Incorporated TLK6002 www. ti. com SLLSE34A ­ MAY 2010 ­ REVISED AUGUST 2010 2. 22. 2 Receive Parallel Output Clock During ARS Mode Per channel ARS_RX_CLK_EN (register bit 10. 15) allows software programmability as to whether the recovered output byte clock (RXCLK_A/B) is allowed to toggle (dynamically changing rates as the ARS rate determination process executes), or if it is held fixed to zero until the incoming serial rate for the channel has been determined. At the time rate determination is successful, the receive parallel output interface clock is automatically allowed to toggle if it was prevented from toggling during ARS (and enabling toggling is not delayed or gated by MDIO interaction in the case where ARS_TX_MDIO_GATE is asserted). Reset | (6. 6 & LOS(Loss of Signal)) No Comma Loss Of Sync (Enable Alignment) Sync Status Not Ok Comma Comma Detect 1 (Disable Alignment) Invalid Decode Comma !Comma & !Invalid Decode Comma Detect 2 Invalid Decode Comma !Comma & !Invalid Decode Comma Detect 3 Invalid Decode Comma A Sync Acquired 1 (Sync Status Ok) Invalid B Decode Sync Acquired 2 (good cgs = 0) C Invalid Decode Sync Acquired 3 (good cgs = 0) Invalid Decode Sync Acquired 4 (good cgs = 0) Invalid Decode !Comma & !Invalid Decode Note: If CH_SYNC_HYSTERESIS[1:0] (3. 12:11) is equal to 2'b00), machine operates as drawn. If CH_SYNC_HYSTERESIS[1:0] (3. 12:11) is equal to 2'b01/ 2'b10/2'b11, then a transition from all Sync Acquired states occurs immediately upon detection of 1, 2, or 3 adjacent invalid code words or disparity errors respectively. !Invalid Decode Invalid Decode Sync Acquired 2A good cgs++ !invalid Decode & A good_cgs=3 Sync Acquired 3A good cgs++ B !invalid Decode & good_cgs=3 !Invalid Decode& good_cgs !=3 !Invalid Decode Invalid Decode !Invalid Decode & good_cgs !=3 !Invalid Decode Invalid Decode Sync Acquired 4A good cgs++ !invalid Decode& C good_cgs=3 !Invalid Decode & good_cgs !=3 Figure 2-14. Channel Synchronization Flowchart Copyright © 2010, Texas Instruments Incorporated Description Submit Documentation Feedback Product Folder Link(s): TLK6002 39 TLK6002 SLLSE34A ­ MAY 2010 ­ REVISED AUGUST 2010 www. ti. com 2. 23 Output Clock Selection (CLK_OUT_P/N) Table 2-9 details CLK_OUT_P/N as a function of device settings. CLK_OUT_P/N Frequencies (ARS Enabled and Disabled) RATE_A[2:0] 000/001/010/011 000/001/010/011 110 110 110 110 Not 110 Not 110 Not 110 Not 110 101 101 101 101 101 000/001/010/011 000/001/010/011 000/001/010/011 000/001/010/011 000/001/010/011 101 101 101 101 101 101 101 101 111 111 111 111 111 111 101/110 101/110 101/110 101/110 000/001/010/011/111 000/001/010/011/111 RATE_B[2:0] 000/001/010/011 000/001/010/011 Not 110 Not 110 Not 110 Not 110 110 110 110 110 000/001/010/011 000/001/010/011 000/001/010/011 000/001/010/011 000/001/010/011 101 101 101 101 101 101 101 101 101 101 101 101 101 101/110 101/110 101/110 101/110 000/001/010/011/111 000/001/010/011/111 111 111 111 111 111 111 CLK_OUT_SEL 0 1 x x x x x x x x 0 0 0 0 1 1 1 1 1 0 0 0 0 0 1 1 1 1 x x x x 0 1 x x x x 0 1 CLK_OUT_P/N RXBCLK_A/(0. 5:4) RXBCLK_B/(0. 5:4) 153. 6 MHz (ppm 0 to RXAP/N) 61. 44 MHz (ppm 0 to RXAP/N) 153. 6 MHz (ppm 0 to RXAP/N) 61. 44 MHz (ppm 0 to RXAP/N) 153. 6 MHz (ppm 0 to RXBP/N) 61. 44 MHz (ppm 0 to RXBP/N) 153. 6 MHz (ppm 0 to RXBP/N) 61. 44 MHz (ppm 0 to RXBP/N) 153. 6 MHz (ppm 0 to RXAP/N) 61. 44 MHz (ppm 0 to RXAP/N) 153. 6 MHz (ppm 0 to RXAP/N) 61. 44 MHz (ppm 0 to RXAP/N) RXBCLK_B/(0. 5:4) 153. 6 MHz (ppm 0 to RXBP/N) 61. 44 MHz (ppm 0 to RXBP/N) 153. 6 MHz (ppm 0 to RXBP/N) 61. 44 MHz (ppm 0 to RXBP/N) RXBCLK_A/(0. 5:4) 153. 6 MHz (ppm 0 to RXAP/N) 61. 44 MHz (ppm 0 to RXAP/N) 153. 6 MHz (ppm 0 to RXAP/N) 61. 44 MHz (ppm 0 to RXAP/N) 153. 6 MHz (ppm 0 to RXBP/N) 61. 44 MHz (ppm 0 to RXBP/N) 153. 6 MHz (ppm 0 to RXBP/N) 61. 44 MHz (ppm 0 to RXBP/N) 153. 6 MHz (ppm 0 to RXBP/N) 61. 44 MHz (ppm 0 to RXBP/N) 153. 6 MHz (ppm 0 to RXBP/N) 61. 44 MHz (ppm 0 to RXBP/N) RXBCLK_A/(0. 5:4) RXBCLK_B/(0. 5:4) 153. 6 MHz (ppm 0 to RXAP/N) 61. 44 MHz (ppm 0 to RXAP/N) 153. 6 MHz (ppm 0 to RXAP/N) 61. 44 MHz (ppm 0 to RXAP/N) RXBCLK_A/(0. 5:4) RXBCLK_B/(0. 5:4) Selected Channel A REFCLK Frequency (MHz) Indicated By ARS_REF_FREQ x x 153. 6 122. 88 307. 2 245. 76 x x x x 153. 6 122. 88 307. 2 245. 76 x x x x x x 153. 6 122. 88 307. 2 245. 76 x x x x x x x x x x 153. 6 122. 88 307. 2 245. 76 x x Selected Channel B REFCLK Frequency (MHz) Indicated By ARS_REF_FREQ x x x x x x 153. 6 122. 88 307. 2 245. 76 x x x x x 153. 6 122. 88 307. 2 245. 76 x x x x x 153. 6 122. 88 307. 2 245. 76 153. 6 122. 88 307. 2 245. 76 x x x x x x x x 2. 24 MDIO Management Interface The TLK6002 supports the Management Data Input/Output (MDIO) Interface as defined in Clause 22 of the IEEE 802. 3 Ethernet specification. The MDIO allows register-based management and control of the serial links. Normal operation of the TLK6002 is possible without use of this interface. [. . . ] In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. [. . . ]