User manual TEXAS INSTRUMENTS STELLARIS LM3S1R21 DATA SHEET

[. . . ] TE X AS I NS TRUM E NTS - ADVANCE I NFO RMAT ION Stellaris® LM3S1R21 Microcontroller D ATA SHE E T D S -LM 3S 1R 21 - 6 7 9 0 C opyri ght © 2007-2010 Texas Instruments Incorporated Copyright Copyright © 2007-2010 Texas Instruments Incorporated All rights reserved. Stellaris and StellarisWare are registered trademarks of Texas Instruments Incorporated. ARM and Thumb are registered trademarks and Cortex is a trademark of ARM Limited. ADVANCE INFORMATION concerns new products in the sampling or preproduction phase of development. [. . . ] If a bit in the GPIOCR register is set, the data being written to the corresponding bit of the GPIOAFSEL, GPIOPUR, GPIOPDR, or GPIODEN registers is committed to the register and reflects the new value. The contents of the GPIOCR register can only be modified if the status in the GPIOLOCK register is unlocked. Writes to the GPIOCR register are ignored if the status in the GPIOLOCK register is locked. Important: This register is designed to prevent accidental programming of the registers that control connectivity to the NMI and JTAG/SWD debug hardware. By initializing the bits of the GPIOCR register to 0 for PB7 and PC[3:0], the NMI and JTAG/SWD debug port can only be converted to GPIOs through a deliberate set of writes to the GPIOLOCK, GPIOCR, and the corresponding registers. Because this protection is currently only implemented on the NMI and JTAG/SWD pins on PB7 and PC[3:0], all of the other bits in the GPIOCR registers cannot be written with 0x0. These bits are hardwired to 0x1, ensuring that it is always possible to commit new values to the GPIOAFSEL, GPIOPUR, GPIOPDR, or GPIODEN register bits of these other pins. GPIO Commit (GPIOCR) GPIO Port A (APB) base: 0x4000. 4000 GPIO Port A (AHB) base: 0x4005. 8000 GPIO Port B (APB) base: 0x4000. 5000 GPIO Port B (AHB) base: 0x4005. 9000 GPIO Port C (APB) base: 0x4000. 6000 GPIO Port C (AHB) base: 0x4005. A000 GPIO Port D (APB) base: 0x4000. 7000 GPIO Port D (AHB) base: 0x4005. B000 GPIO Port E (APB) base: 0x4002. 4000 GPIO Port E (AHB) base: 0x4005. C000 GPIO Port F (APB) base: 0x4002. 5000 GPIO Port F (AHB) base: 0x4005. D000 GPIO Port G (APB) base: 0x4002. 6000 GPIO Port G (AHB) base: 0x4005. E000 GPIO Port H (APB) base: 0x4002. 7000 GPIO Port H (AHB) base: 0x4005. F000 GPIO Port J (APB) base: 0x4003. D000 GPIO Port J (AHB) base: 0x4006. 0000 Offset 0x524 Type -, reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 CR RO 0 RO 0 RO 0 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 February 09, 2010 Texas Instruments-Advance Information 329 General-Purpose Input/Outputs (GPIOs) Bit/Field 31:8 Name reserved Type RO Reset 0x0000. 00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPIO Commit Value Description 1 0 The corresponding GPIOAFSEL, GPIOPUR, GPIOPDR, or GPIODEN bits can be written. The corresponding GPIOAFSEL, GPIOPUR, GPIOPDR, or GPIODEN bits cannot be written. The default register type for the GPIOCR register is RO for all GPIO pins with the exception of the NMI pin and the four JTAG/SWD pins (PB7 and PC[3:0]). These five pins are currently the only GPIOs that are protected by the GPIOCR register. Because of this, the register type for GPIO Port B7 and GPIO Port C[3:0] is R/W. The default reset value for the GPIOCR register is 0x0000. 00FF for all GPIO pins, with the exception of the NMI pin and the four JTAG/SWD pins (PB7 and PC[3:0]). To ensure that the JTAG port is not accidentally programmed as a GPIO, these four pins default to non-committable. To ensure that the NMI pin is not accidentally programmed as the non-maskable interrupt pin, it defaults to non-committable. Because of this, the default reset value of GPIOCR for GPIO Port B is 0x0000. 007F while the default reset value of GPIOCR for Port C is 0x0000. 00F0. 7:0 CR - - Note: 330 Texas Instruments-Advance Information February 09, 2010 Stellaris® LM3S1R21 Microcontroller Register 21: GPIO Analog Mode Select (GPIOAMSEL), offset 0x528 Important: This register is only valid for ports D and E; the corresponding base addresses for the remaining ports are not valid. If any pin is to be used as an ADC input, the appropriate bit in GPIOAMSEL must be set to disable the analog isolation circuit. The GPIOAMSEL register controls isolation circuits to the analog side of a unified I/O pad. Because the GPIOs may be driven by a 5-V source and affect analog operation, analog circuitry requires isolation from the pins when they are not used in their analog function. Each bit of this register controls the isolation circuitry for the corresponding GPIO signal. For information on which GPIO pins can be used for ADC functions, refer to Table 20-5 on page 741. GPIO Analog Mode Select (GPIOAMSEL) GPIO Port A (APB) base: 0x4000. 4000 GPIO Port A (AHB) base: 0x4005. 8000 GPIO Port B (APB) base: 0x4000. 5000 GPIO Port B (AHB) base: 0x4005. 9000 GPIO Port C (APB) base: 0x4000. 6000 GPIO Port C (AHB) base: 0x4005. A000 GPIO Port D (APB) base: 0x4000. 7000 GPIO Port D (AHB) base: 0x4005. B000 GPIO Port E (APB) base: 0x4002. 4000 GPIO Port E (AHB) base: 0x4005. C000 GPIO Port F (APB) base: 0x4002. 5000 GPIO Port F (AHB) base: 0x4005. D000 GPIO Port G (APB) base: 0x4002. 6000 GPIO Port G (AHB) base: 0x4005. E000 GPIO Port H (APB) base: 0x4002. 7000 GPIO Port H (AHB) base: 0x4005. F000 GPIO Port J (APB) base: 0x4003. D000 GPIO Port J (AHB) base: 0x4006. 0000 Offset 0x528 Type R/W, reset 0x0000. 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 reserved R/W 0 RO 0 RO 0 RO 0 RO 0 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 GPIOAMSEL R/W 0 R/W 0 Bit/Field 31:8 Name reserved Type RO Reset 0x0000. 00 Description Software should not rely on the value of a reserved bit. [. . . ] 108-Ball BGA Package 854 Texas Instruments-Advance Information February 09, 2010 Stellaris® LM3S1R21 Microcontroller Note: The following notes apply to the package drawing. Symbols A A1 A3 c D D1 E E1 b bbb ddd e f M n MIN 1. 22 0. 29 0. 65 0. 28 9. 85 NOM 1. 36 0. 34 0. 70 0. 32 10. 00 8. 80 BSC MAX 1. 50 0. 39 0. 75 0. 36 10. 15 9. 85 10. 00 8. 80 BSC 10. 15 0. 43 0. 48 . 20 . 12 0. 80 BSC 0. 53 - 0. 60 12 108 REF: JEDEC MO-219F - February 09, 2010 Texas Instruments-Advance Information 855 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. 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