User manual TEXAS INSTRUMENTS STELLARIS LM3S1162 DATA SHEET REV D

[. . . ] TE X AS INS TRUM E NTS - P RO DUCTI O N D ATA Stellaris® LM3S1162 Microcontroller D ATA SHE E T D S -LM 3S 1162 - 7 3 9 3 C opyri ght © 2007-2010 Texas Instr uments Incor porated Copyright Copyright © 2007-2010 Texas Instruments Incorporated All rights reserved. Stellaris and StellarisWare are registered trademarks of Texas Instruments Incorporated. ARM and Thumb are registered trademarks and Cortex is a trademark of ARM Limited. Products conform to specifications per the terms of Texas Instruments standard warranty. [. . . ] GPIODATA Write Example ADDR[9:2] 0x098 0xEB GPIODATA 9 0 8 0 7 1 6 0 5 0 4 1 3 1 2 0 1 0 0 0 1 1 1 0 1 0 1 1 u 7 u 6 1 5 u 4 u 3 0 2 1 1 u 0 During a read, if the address bit associated with the data bit is set to 1, the value is read. If the address bit associated with the data bit is set to 0, it is read as a zero, regardless of its actual value. For example, reading address GPIODATA + 0x0C4 yields as shown in Figure 9-3 on page 179. GPIODATA Read Example ADDR[9:2] 0x0C4 GPIODATA Returned Value 9 0 8 0 7 1 6 1 5 0 4 0 3 0 2 1 1 0 0 0 1 0 1 1 1 1 1 0 0 7 0 6 1 5 1 4 0 3 0 2 0 1 0 0 9. 1. 2 Interrupt Control The interrupt capabilities of each GPIO port are controlled by a set of seven registers. With these registers, it is possible to select the source of the interrupt, its polarity, and the edge properties. When one or more GPIO inputs cause an interrupt, a single interrupt output is sent to the interrupt controller for the entire GPIO port. For edge-triggered interrupts, software must clear the interrupt to enable any further interrupts. For a level-sensitive interrupt, it is assumed that the external source holds the level constant for the interrupt to be recognized by the controller. Three registers are required to define the edge or sense that causes interrupts: GPIO Interrupt Sense (GPIOIS) register (see page 187) GPIO Interrupt Both Edges (GPIOIBE) register (see page 188) GPIO Interrupt Event (GPIOIEV) register (see page 189) Interrupts are enabled/disabled via the GPIO Interrupt Mask (GPIOIM) register (see page 190). When an interrupt condition occurs, the state of the interrupt signal can be viewed in two locations: the GPIO Raw Interrupt Status (GPIORIS) and GPIO Masked Interrupt Status (GPIOMIS) registers (see page 191 and page 192). As the name implies, the GPIOMIS register only shows interrupt June 23, 2010 Texas Instruments-Production Data 179 General-Purpose Input/Outputs (GPIOs) conditions that are allowed to be passed to the controller. The GPIORIS register indicates that a GPIO pin meets the conditions for an interrupt, but has not necessarily been sent to the controller. In addition to providing GPIO functionality, PB4 can also be used as an external trigger for the ADC. If PB4 is configured as a non-masked interrupt pin (the appropriate bit of GPIOIM is set to 1), not only is an interrupt for PortB generated, but an external trigger signal is sent to the ADC. If the ADC Event Multiplexer Select (ADCEMUX) register is configured to use the external trigger, an ADC conversion is initiated. If no other PortB pins are being used to generate interrupts, the ARM Integrated Nested Vectored Interrupt Controller (NVIC) Interrupt Set Enable (SETNA) register can disable the PortB interrupts and the ADC interrupt can be used to read back the converted data. Otherwise, the PortB interrupt handler needs to ignore and clear interrupts on B4, and wait for the ADC interrupt or the ADC interrupt needs to be disabled in the SETNA register and the PortB interrupt handler polls the ADC registers until the conversion is completed. Interrupts are cleared by writing a 1 to the appropriate bit of the GPIO Interrupt Clear (GPIOICR) register (see page 193). When programming the following interrupt control registers, the interrupts should be masked (GPIOIM set to 0). Writing any value to an interrupt control register (GPIOIS, GPIOIBE, or GPIOIEV) can generate a spurious interrupt if the corresponding bits are enabled. 9. 1. 3 Mode Control The GPIO pins can be controlled by either hardware or software. When hardware control is enabled via the GPIO Alternate Function Select (GPIOAFSEL) register (see page 194), the pin state is controlled by its alternate function (that is, the peripheral). Software control corresponds to GPIO mode, where the GPIODATA register is used to read/write the corresponding pins. 9. 1. 4 Commit Control The GPIO commit control registers provide a layer of protection against accidental programming of critical hardware peripherals. [. . . ] 108-Ball BGA Package June 23, 2010 Texas Instruments-Production Data 551 Package Information Note: The following notes apply to the package drawing. Symbols A A1 A3 c D D1 E E1 b bbb ddd e f M n MIN 1. 22 0. 29 0. 65 0. 28 9. 85 NOM 1. 36 0. 34 0. 70 0. 32 10. 00 8. 80 BSC MAX 1. 50 0. 39 0. 75 0. 36 10. 15 9. 85 10. 00 8. 80 BSC 10. 15 0. 43 0. 48 . 20 . 12 0. 80 BSC 0. 53 - 0. 60 12 108 REF: JEDEC MO-219F - 552 Texas Instruments-Production Data June 23, 2010 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. [. . . ]