User manual TEXAS INSTRUMENTS STELLARIS LM3S1110 MICROCONTROLLER DATASHEET

[. . . ] TE X AS INS TRUM E NTS - P RO DUCTI O N D ATA Stellaris® LM3S1110 Microcontroller D ATA SHE E T D S -LM 3S 1110 - 7 7 8 7 C opyri ght © 2007-2010 Texas Instr uments Incor porated Copyright Copyright © 2007-2010 Texas Instruments Incorporated All rights reserved. Stellaris and StellarisWare are registered trademarks of Texas Instruments Incorporated. ARM and Thumb are registered trademarks and Cortex is a trademark of ARM Limited. Products conform to specifications per the terms of Texas Instruments standard warranty. [. . . ] This loop can be removed for production software as the DAP is most likely not enabled during normal execution. Because the DAP is disabled by default (power on reset), the user can also power-cycle the device. The DAP is not enabled unless it is enabled through the JTAG or SWD interface. 5. 2 Initialization and Configuration The PLL is configured using direct register writes to the RCC/RCC2 register. If the RCC2 register is being used, the USERCC2 bit must be set and the appropriate RCC2 bit/field is used. The steps required to successfully change the PLL-based system clock are: 1. Bypass the PLL and system clock divider by setting the BYPASS bit and clearing the USESYS bit in the RCC register. This configures the system to run off a "raw" clock source and allows for the new PLL configuration to be validated before switching the system clock to the PLL. Select the crystal value (XTAL) and oscillator source (OSCSRC), and clear the PWRDN bit in RCC/RCC2. Setting the XTAL field automatically pulls valid PLL configuration data for the appropriate crystal, and clearing the PWRDN bit powers and enables the PLL and its output. Select the desired system divider (SYSDIV) in RCC/RCC2 and set the USESYS bit in RCC. The SYSDIV field determines the system frequency for the microcontroller. Wait for the PLL to lock by polling the PLLLRIS bit in the Raw Interrupt Status (RIS) register. Enable use of the PLL by clearing the BYPASS bit in RCC/RCC2. 5. 3 Register Map Table 5-4 on page 171 lists the System Control registers, grouped by function. The offset listed is a hexadecimal increment to the register's address, relative to the System Control base address of 0x400F. E000. 170 Texas Instruments-Production Data September 04, 2010 Stellaris® LM3S1110 Microcontroller Note: Spaces in the System Control register space that are not used are reserved for future or internal use. System Control Register Map Offset 0x000 0x004 0x008 0x010 0x014 0x018 0x01C 0x030 0x034 0x040 0x044 0x048 0x050 0x054 0x058 0x05C 0x060 0x064 0x070 0x100 0x104 0x108 0x110 0x114 0x118 0x120 0x124 0x128 0x144 Name DID0 DID1 DC0 DC1 DC2 DC3 DC4 PBORCTL LDOPCTL SRCR0 SRCR1 SRCR2 RIS IMC MISC RESC RCC PLLCFG RCC2 RCGC0 RCGC1 RCGC2 SCGC0 SCGC1 SCGC2 DCGC0 DCGC1 DCGC2 DSLPCLKCFG Type RO RO RO RO RO RO RO R/W R/W R/W R/W R/W RO R/W R/W1C R/W R/W RO R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0x003F. 001F 0x0000. 70DF 0x0307. 0013 0x8300. 0FC0 0x0000. 00FF 0x0000. 7FFD 0x0000. 0000 0x00000000 0x00000000 0x00000000 0x0000. 0000 0x0000. 0000 0x0000. 0000 0x0780. 3AD1 0x0780. 2810 0x00000040 0x00000000 0x00000000 0x00000040 0x00000000 0x00000000 0x00000040 0x00000000 0x00000000 0x0780. 0000 Description Device Identification 0 Device Identification 1 Device Capabilities 0 Device Capabilities 1 Device Capabilities 2 Device Capabilities 3 Device Capabilities 4 Brown-Out Reset Control LDO Power Control Software Reset Control 0 Software Reset Control 1 Software Reset Control 2 Raw Interrupt Status Interrupt Mask Control Masked Interrupt Status and Clear Reset Cause Run-Mode Clock Configuration XTAL to PLL Translation Run-Mode Clock Configuration 2 Run Mode Clock Gating Control Register 0 Run Mode Clock Gating Control Register 1 Run Mode Clock Gating Control Register 2 Sleep Mode Clock Gating Control Register 0 Sleep Mode Clock Gating Control Register 1 Sleep Mode Clock Gating Control Register 2 Deep Sleep Mode Clock Gating Control Register 0 Deep Sleep Mode Clock Gating Control Register 1 Deep Sleep Mode Clock Gating Control Register 2 Deep Sleep Clock Configuration See page 173 188 190 191 193 195 197 175 176 213 214 216 177 178 179 180 181 184 185 198 201 207 199 203 209 200 205 211 187 September 04, 2010 Texas Instruments-Production Data 171 System Control 5. 4 Register Descriptions All addresses given are relative to the System Control base address of 0x400F. E000. 172 Texas Instruments-Production Data September 04, 2010 Stellaris® LM3S1110 Microcontroller Register 1: Device Identification 0 (DID0), offset 0x000 This register identifies the version of the device. Device Identification 0 (DID0) Base 0x400F. E000 Offset 0x000 Type RO, reset 31 reserved 30 29 VER 28 27 26 25 24 23 22 21 20 CLASS 19 18 17 16 reserved RO 1 12 MAJOR RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 3 MINOR RO 0 2 RO 0 1 RO 1 0 Type Reset RO - RO - RO - RO - RO - RO - RO - RO - RO - RO - RO - RO - RO - RO - RO - RO - Bit/Field 31 Name reserved Type RO Reset 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. The value of the VER field is encoded as follows: Value Description 0x1 Second version of the DID0 register format. 30:28 VER RO 0x1 27:24 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Device Class The CLASS field value identifies the internal design from which all mask sets are generated for all devices in a particular product line. The CLASS field value is changed for new product lines, for changes in fab process (for example, a remap or shrink), or any case where the MAJOR or MINOR fields require differentiation from prior devices. The value of the CLASS field is encoded as follows (all other encodings are reserved): Value Description 0x1 Stellaris® Fury-class devices. 23:16 CLASS RO 0x1 September 04, 2010 Texas Instruments-Production Data 173 System Control Bit/Field 15:8 Name MAJOR Type RO Reset - Description Major Revision This field specifies the major revision number of the device. The major revision number is indicated in the part number as a letter (A for first revision, B for second, and so on). [. . . ] 100-Pin LQFP Tape and Reel Dimensions THIS IS A COMPUTER GENERATED UNCONTROLLED DOCUMENT PRINTED ON 06. 01. 2003 06. 01. 2003 06. 01. 2003 MUST NOT BE REPRODUCED WITHOUT WRITTEN PERMISSION FROM SUMICARRIER (S) PTE LTD 06. 01. 2003 06. 01. 2003 September 04, 2010 Texas Instruments-Production Data 523 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. [. . . ]