User manual TEXAS INSTRUMENTS AM1705 ARM MICROPROCESSOR FEATURES 10-2010

[. . . ] AM1705 www. ti. com SPRS657B ­ FEBRUARY 2010 ­ REVISED OCTOBER 2010 AM1705 ARM Microprocessor Check for Samples: AM1705 1 AM1705 ARM Microprocessor 1. 1 123 Features ­ 32 Independent DMA Channels ­ 8 Quick DMA Channels ­ Programmable Transfer Burst Size 128K-Byte RAM Memory 3. 3V LVCMOS IOs (except for USB interface) Two External Memory Interfaces: ­ EMIFA · NOR (8-Bit-Wide Data) ­ EMIFB · 16-Bit SDRAM With 256MB Address Space Three Configurable 16550 type UART Modules: ­ UART0 With Modem Control Signals ­ 16-byte FIFO ­ 16x or 13x Oversampling Option ­ Autoflow control signals (CTS, RTS) on UART0 only Two Serial Peripheral Interfaces (SPI) Each With One Chip-Select Programmable Real-Time Unit Subsystem (PRUSS) ­ Two Independent Programmable Realtime Unit (PRU) Cores · 32-Bit Load/Store RISC architecture · 4K Byte instruction RAM per core · 512 Bytes data RAM per core · PRU Subsystem (PRUSS) can be disabled via software to save power ­ Standard power management mechanism · Clock gating · Entire subsystem under a single PSC clock gating domain ­ Dedicated interrupt controller ­ Dedicated switched central resource Multimedia Card (MMC)/Secure Digital (SD) Card Interface with Secure Data I/O (SDIO) Two Master/Slave Inter-Integrated Circuit (I2C BusTM) USB 2. 0 OTG Port With Integrated PHY (USB0) ­ USB 2. 0 Full-Speed Client ­ USB 2. 0 Full-/Low-Speed Host · Highlights ­ 375/456-MHz ARM926EJ-STM RISC Core ­ ARM9 Memory Architecture ­ Programmable Real-Time Unit Subsystem ­ Enhanced Direct-Memory-Access Controller 3 (EDMA3) ­ Two External Memory Interfaces ­ Three Configurable 16550 type UART Modules ­ Two Serial Peripheral Interfaces (SPI) ­ Multimedia Card (MMC)/Secure Digital (SD) Card Interface with Secure Data I/O (SDIO) ­ Two Master/Slave Inter-Integrated Circuit ­ USB 2. 0 OTG Port With Integrated PHY ­ Two Multichannel Audio Serial Ports ­ 10/100 Mb/s Ethernet MAC (EMAC) ­ One 64-Bit General-Purpose Timer ­ One 64-bit General-Purpose/Watchdog Timer ­ Three Enhanced Pulse Width Modulators ­ Three 32-Bit Enhanced Capture Modules · Applications ­ Industrial Automation ­ Home Automation ­ Test and Measurement ­ Portable Data Terminals ­ Educational Consoles ­ Power Protection Systems · 375/456-MHz ARM926EJ-STM RISC Core ­ 32-Bit and 16-Bit (Thumb®) Instructions ­ Single Cycle MAC ­ ARM® Jazelle® Technology ­ EmbeddedICE-RTTM for Real-Time Debug · ARM9 Memory Architecture ­ 16K-Byte Instruction Cache ­ 16K-Byte Data Cache ­ 8K-Byte RAM (Vector Table) ­ 64K-Byte ROM · Enhanced Direct-Memory-Access Controller 3 (EDMA3): ­ 2 Transfer Controllers 1 · · · · · · · · · 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. ARM926EJ-S, EmbeddedICE-RT, ETM9, CoreSight are trademarks of ARM Limited. ARM, Jazelle are registered trademarks of ARM Limited. Copyright © 2010, Texas Instruments Incorporated ADVANCE INFORMATION concerns new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice. ADVANCE INFORMATION AM1705 SPRS657B ­ FEBRUARY 2010 ­ REVISED OCTOBER 2010 www. ti. com · · · · · ­ End Point 0 (Control) ­ End Points 1, 2, 3, 4 (Control, Bulk, Interrupt or ISOC) Rx and Tx Two Multichannel Audio Serial Ports: ­ Six Clock Zones and 28 Serial Data Pins ­ Supports TDM, I2S, and Similar Formats ­ FIFO buffers for Transmit and Receive 10/100 Mb/s Ethernet MAC (EMAC): ­ IEEE 802. 3 Compliant (3. 3-V I/O Only) ­ RMII Media Independent Interface ­ Management Data I/O (MDIO) Module One 64-Bit General-Purpose Timer (Configurable as Two 32-Bit Timers) One 64-bit General-Purpose/Watchdog Timer (Configurable as Two 32-bit General-Purpose Timers) Three Enhanced Pulse Width Modulators (eHRPWM): ­ Dedicated 16-Bit Time-Base Counter With Period And Frequency Control · · · · · ­ 6 Single Edge, 6 Dual Edge Symmetric or 3 Dual Edge Asymmetric Outputs ­ Dead-Band Generation ­ PWM Chopping by High-Frequency Carrier ­ Trip Zone Input Three 32-Bit Enhanced Capture Modules (eCAP): ­ Configurable as 3 Capture Inputs or 3 Auxiliary Pulse Width Modulator (APWM) outputs ­ Single Shot Capture of up to Four Event Time-Stamps Two 32-Bit Enhanced Quadrature Encoder Pulse Modules (eQEP) 176-pin PowerPADTM Plastic Quad Flat Pack [PTP suffix], 0. 5-mm Pin Pitch Commercial, Industrial, or Extended Temperature Community Resources ­ TI E2E Community ­ TI Embedded Processors Wiki ADVANCE INFORMATION 2 AM1705 ARM Microprocessor Submit Documentation Feedback Product Folder Link(s): AM1705 Copyright © 2010, Texas Instruments Incorporated AM1705 www. ti. com SPRS657B ­ FEBRUARY 2010 ­ REVISED OCTOBER 2010 1. 2 Trademarks All trademarks are the property of their respective owners. Copyright © 2010, Texas Instruments Incorporated AM1705 ARM Microprocessor Submit Documentation Feedback Product Folder Link(s): AM1705 3 ADVANCE INFORMATION AM1705 SPRS657B ­ FEBRUARY 2010 ­ REVISED OCTOBER 2010 www. ti. com 1. 3 Description The device is a low-power ARM microprocessor based on an ARM926EJ-STM. [. . . ] This allows a single handshake line to be shared by multiple slaves on the same SPI bus. In master mode, the SPIx_ENA pin is an optional input and the master can be configured to delay the start of the next transfer until the slave asserts SPIx_ENA. The addition of this handshake signal simplifies SPI communications and, on average, increases SPI bus throughput since the master does not need to delay each transfer long enough to allow for the worst-case latency of the slave device. Instead, each transfer can begin as soon as both the master and slave have actually serviced the previous SPI transfer. Although the SPI module supports two interrupt outputs, SPIx_INT1 is the only interrupt connected on this device. ADVANCE INFORMATION 96 Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): AM1705 Copyright © 2010, Texas Instruments Incorporated AM1705 www. ti. com SPRS657B ­ FEBRUARY 2010 ­ REVISED OCTOBER 2010 Optional - Slave Chip Select SPIx_SCS Optional Enable (Ready) SPIx_ENA SPIx_ENA SPIx_SCS SPIx_CLK SPIx_CLK SPIx_SOMI SPIx_SOMI SPIx_SIMO SPIx_SIMO MASTER SPI SLAVE SPI Figure 6-31. Illustration of SPI Master-to-SPI Slave Connection Copyright © 2010, Texas Instruments Incorporated Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): AM1705 97 ADVANCE INFORMATION AM1705 SPRS657B ­ FEBRUARY 2010 ­ REVISED OCTOBER 2010 www. ti. com 6. 18. 1 SPI Peripheral Registers Description(s) Table 6-48 is a list of the SPI registers. SPIx Configuration Registers SPI0 BYTE ADDRESS 0x01C4 1000 0x01C4 1004 0x01C4 1008 0x01C4 100C 0x01C4 1010 0x01C4 1014 0x01C4 1018 0x01C4 101C 0x01C4 1020 0x01C4 1024 0x01C4 1028 0x01C4 102C 0x01C4 1030 0x01C4 1034 0x01C4 1038 0x01C4 103C 0x01C4 1040 0x01C4 1044 0x01C4 1048 0x01C4 104C 0x01C4 1050 0x01C4 1054 0x01C4 1058 0x01C4 105C 0x01C4 1060 0x01C4 1064 SPI1 BYTE ADDRESS 0x01E1 2000 0x01E1 2004 0x01E1 2008 0x01E1 200C 0x01E1 2010 0x01E1 2014 0x01E1 2018 0x01E1 201C 0x01E1 2020 0x01E1 2024 0x01E1 2028 0x01E1 202C 0x01E1 2030 0x01E1 2034 0x01E1 2038 0x01E1 203C 0x01E1 2040 0x01E1 2044 0x01E1 2048 0x01E1 204C 0x01E1 2050 0x01E1 2054 0x01E1 2058 0x01E1 205C 0x01E1 2060 0x01E1 2064 ACRONYM SPIGCR0 SPIGCR1 SPIINT0 SPILVL SPIFLG SPIPC0 SPIPC1 SPIPC2 SPIPC3 SPIPC4 SPIPC5 Reserved Reserved Reserved SPIDAT0 SPIDAT1 SPIBUF SPIEMU SPIDELAY SPIDEF SPIFMT0 SPIFMT1 SPIFMT2 SPIFMT3 Reserved INTVEC1 REGISTER DESCRIPTION Global Control Register 0 Global Control Register 1 Interrupt Register Interrupt Level Register Flag Register Pin Control Register 0 (Pin Function) Pin Control Register 1 (Pin Direction) Pin Control Register 2 (Pin Data In) Pin Control Register 3 (Pin Data Out) Pin Control Register 4 (Pin Data Set) Pin Control Register 5 (Pin Data Clear) Reserved - Do not write to this register Reserved - Do not write to this register Reserved - Do not write to this register Shift Register 0 (without format select) Shift Register 1 (with format select) Buffer Register Emulation Register Delay Register Default Chip Select Register Format Register 0 Format Register 1 Format Register 2 Format Register 3 Reserved - Do not write to this register Interrupt Vector for SPI INT1 ADVANCE INFORMATION 98 Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): AM1705 Copyright © 2010, Texas Instruments Incorporated AM1705 www. ti. com SPRS657B ­ FEBRUARY 2010 ­ REVISED OCTOBER 2010 6. 18. 2 SPI Electrical Data/Timing 6. 18. 2. 1 Serial Peripheral Interface (SPI) Timing Table 6-49 through Table 6-64 assume testing over recommended operating conditions (see Figure 6-32 through Figure 6-35). 1 2 3 tc(SPC)M tw(SPCH)M tw(SPCL)M PARAMETER Cycle Time, SPI0_CLK, All Master Modes Pulse Width High, SPI0_CLK, All Master Modes Pulse Width Low, SPI0_CLK, All Master Modes Polarity = 0, Phase = 0, to SPI0_CLK rising Delay, initial data bit valid on SPI0_SIMO after initial edge on SPI0_CLK (2) Polarity = 0, Phase = 1, to SPI0_CLK rising Polarity = 1, Phase = 0, to SPI0_CLK falling Polarity = 1, Phase = 1, to SPI0_CLK falling Polarity = 0, Phase = 0, from SPI0_CLK rising Delay, subsequent bits valid on SPI0_SIMO after transmit edge of SPI0_CLK Polarity = 0, Phase = 1, from SPI0_CLK falling Polarity = 1, Phase = 0, from SPI0_CLK falling Polarity = 1, Phase = 1, from SPI0_CLK rising Polarity = 0, Phase = 0, from SPI0_CLK falling Output hold time, SPI0_SIMO valid afterreceive edge of SPI0_CLK Polarity = 0, Phase = 1, from SPI0_CLK rising Polarity = 1, Phase = 0, from SPI0_CLK rising Polarity = 1, Phase = 1, from SPI0_CLK falling Polarity = 0, Phase = 0, to SPI0_CLK falling Input Setup Time, SPI0_SOMI valid beforereceive edge of SPI0_CLK Polarity = 0, Phase = 1, to SPI0_CLK rising Polarity = 1, Phase = 0, to SPI0_CLK rising Polarity = 1, Phase = 1, to SPI0_CLK falling Polarity = 0, Phase = 0, from SPI0_CLK falling Input Hold Time, SPI0_SOMI valid after receive edge of SPI0_CLK Polarity = 0, Phase = 1, from SPI0_CLK rising Polarity = 1, Phase = 0, from SPI0_CLK rising Polarity = 1, Phase = 1, from SPI0_CLK falling (1) (2) 0. 5tc(SPC)M -3 0. 5tc(SPC)M -3 ns 0. 5tc(SPC)M -3 0. 5tc(SPC)M -3 0 0 ns 0 0 5 5 ns 5 5 MIN greater of 3P or 20 ns 0. 5tc(SPC)M - 1 0. 5tc(SPC)M - 1 5 - 0. 5tc(SPC)M + 5 ns 5 - 0. 5tc(SPC)M + 5 5 5 ns 5 5 MAX 256P UNIT ns ns ns 4 td(SIMO_SPC)M 5 td(SPC_SIMO)M 6 toh(SPC_SIMO)M 7 tsu(SOMI_SPC)M 8 tih(SPC_SOMI)M P = SYSCLK2 period First bit may be MSB or LSB depending upon SPI configuration. MO(0) refers to first bit and MO(n) refers to last bit output on SPI0_SIMO. MI(0) refers to the first bit input and MI(n) refers to the last bit input on SPI0_SOMI. Copyright © 2010, Texas Instruments Incorporated Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): AM1705 99 ADVANCE INFORMATION AM1705 SPRS657B ­ FEBRUARY 2010 ­ REVISED OCTOBER 2010 www. ti. com Table 6-50. 9 10 11 tc(SPC)S tw(SPCH)S tw(SPCL)S PARAMETER Cycle Time, SPI0_CLK, All Slave Modes Pulse Width High, SPI0_CLK, All Slave Modes Pulse Width Low, SPI0_CLK, All Slave Modes Polarity = 0, Phase = 0, to SPI0_CLK rising Setup time, transmit data written to SPI before initial clock edge from master. (2) (3) MIN greater of 3P or 20 ns 18 18 2P 2P MAX UNIT ns ns ns 12 tsu(SOMI_SPC)S Polarity = 0, Phase = 1, to SPI0_CLK rising Polarity = 1, Phase = 0, to SPI0_CLK falling Polarity = 1, Phase = 1, to SPI0_CLK falling Polarity = 0, Phase = 0, from SPI0_CLK rising ns 2P 2P 18. 5 18. 5 ns 18. 5 18. 5 0. 5tc(SPC)S -3 0. 5tc(SPC)S -3 ns 0. 5tc(SPC)S -3 0. 5tc(SPC)S -3 0 0 ns 0 0 5 5 ns 5 5 13 td(SPC_SOMI)S Delay, subsequent bits valid on SPI0_SOMI after transmit edge of SPI0_CLK Polarity = 0, Phase = 1, from SPI0_CLK falling Polarity = 1, Phase = 0, from SPI0_CLK falling Polarity = 1, Phase = 1, from SPI0_CLK rising Polarity = 0, Phase = 0, from SPI0_CLK falling ADVANCE INFORMATION 14 toh(SPC_SOMI)S Output hold time, SPI0_SOMI valid afte receive edge of SPI0_CLK Polarity = 0, Phase = 1, from SPI0_CLK rising Polarity = 1, Phase = 0, from SPI0_CLK rising Polarity = 1, Phase = 1, from SPI0_CLK falling Polarity = 0, Phase = 0, to SPI0_CLK falling 15 tsu(SIMO_SPC)S Input Setup Time, SPI0_SIMO valid before receive edge of SPI0_CLK Polarity = 0, Phase = 1, to SPI0_CLK rising Polarity = 1, Phase = 0, to SPI0_CLK rising Polarity = 1, Phase = 1, to SPI0_CLK falling Polarity = 0, Phase = 0, from SPI0_CLK falling 16 tih(SPC_SIMO)S Input Hold Time, SPI0_SIMO valid after receive edge of SPI0_CLK Polarity = 0, Phase = 1, from SPI0_CLK rising Polarity = 1, Phase = 0, from SPI0_CLK rising Polarity = 1, Phase = 1, from SPI0_CLK falling (1) (2) (3) P = SYSCLK2 period First bit may be MSB or LSB depending upon SPI configuration. SO(0) refers to first bit and SO(n) refers to last bit output on SPI0_SOMI. SI(0) refers to the first bit input and SI(n) refers to the last bit input on SPI0_SIMO. Measured from the termination of the write of new data to the SPI module, In analyzing throughput requirements, additional internal bus cycles must be accounted for to allow data to be written to the SPI module by the CPU. 100 Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): AM1705 Copyright © 2010, Texas Instruments Incorporated AM1705 www. ti. com SPRS657B ­ FEBRUARY 2010 ­ REVISED OCTOBER 2010 Table 6-51. PARAMETER Polarity = 0, Phase = 0, to SPI0_CLK rising Delay from slave assertion of SPI0_ENA active to first SPI0_CLK from master. (4) Polarity = 0, Phase = 1, to SPI0_CLK rising Polarity = 1, Phase = 0, to SPI0_CLK falling Polarity = 1, Phase = 1, to SPI0_CLK falling Polarity = 0, Phase = 0, from SPI0_CLK falling Max delay for slave to deassert SPI0_ENA after final SPI0_CLK edge to ensure master does not begin the next transfer. (5) Polarity = 0, Phase = 1, from SPI0_CLK falling Polarity = 1, Phase = 0, from SPI0_CLK rising Polarity = 1, Phase = 1, from SPI0_CLK rising (1) (2) (3) (4) (5) MIN (3) MAX 3P + 3 0. 5tc(SPC)M + 3P + 3 UNIT 17 td(ENA_SPC)M ns 3P + 3 0. 5tc(SPC)M + 3P + 3 0. 5tc(SPC)M + P + 5 P+5 ns 0. 5tc(SPC)M + P + 5 P+5 18 td(SPC_ENA)M Table 6-52. PARAMETER Polarity = 0, Phase = 0, to SPI0_CLK rising Delay from SPI0_SCS active to first SPI0_CLK (4) (5) Polarity = 0, Phase = 1, to SPI0_CLK rising Polarity = 1, Phase = 0, to SPI0_CLK falling Polarity = 1, Phase = 1, to SPI0_CLK falling Polarity = 0, Phase = 0, from SPI0_CLK falling Delay from final SPI0_CLK edge to master deasserting SPI0_SCS (6) (7) Polarity = 0, Phase = 1, from SPI0_CLK falling Polarity = 1, Phase = 0, from SPI0_CLK rising Polarity = 1, Phase = 1, from SPI0_CLK rising (1) (2) (3) (4) (5) (6) (7) MIN 2P - 5 0. 5tc(SPC)M + 2P - 5 (3) MAX UNIT 19 td(SCS_SPC)M ns 2P - 5 0. 5tc(SPC)M + 2P - 5 0. 5tc(SPC)M + P - 3 P-3 ns 0. 5tc(SPC)M + P - 3 P-3 20 td(SPC_SCS)M These parameters are in addition to the general timings for SPI master modes (Table 6-49). P = SYSCLK2 period Figure shows only Polarity = 0, Phase = 0 as an example. In the case where the master SPI is ready with new data before SPI0_SCS assertion. This delay can be increased under software control by the register bit field SPIDELAY. C2TDELAY[4:0]. [. . . ] In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. [. . . ]