User manual PQI COMPACTFLASH CARD DATASHEET REV A.1

[. . . ] Datasheet Product CompactFlash Card Part Number 6ACJ-XXXXRXXXX Description CompactFlash Card Release Date 2010. 07. 19 Customer Customer approve Approved LEVEL Person Prepared by DSC10007 Rev. Please sign-off or stamp with company-seal on the Delivery Specification and return the original copy back to PQI. To change Delivery Specification contents or descriptions must be negotiated with PQI in advance. Any changes made will be result in the issuing of a revised version to be signed-off or stamp with company-seal. [. . . ] Card configuration status is reset and the card internal initialized operation starts when Card Hard Reset is executed, so next access to the card should be the same sequence as the power on sequence. This bit sets to "0" when pulse mode interrupt is selected and "1 when level mode interrupt is selected. When Power on, Card Hard Reset and Soft Reset, this data is "000000" for the purpose of Memory card interface recognition. SRESET (HOST->) R/W LevIREQ (HOST->) INDEX (HOST->) R/W R/W Note: initial value 00H INDEX bit assignment INDEX bit 5 0 0 0 0 4 0 0 0 0 3 0 0 0 0 2 0 0 0 0 1 0 0 1 1 0 0 1 0 1 Card mode Memory card I/O card I/O card I/O card Task File register address 0H to FH, 400H to 7FFH ××0H to ××FH 1F0H to 1F7H, 3F6H to 3F7H 170H to 177H, 376H to 377H Mapping mode memory mapped Contiguous I/O mapped Primary I/O mapped Secondary I/O mapped 4. 3. 2 Configuration and Status register (Address 202H) This register is used for observing the card state. bit7 CHGED bit6 SIGCHG bit5 IOIS8 bit4 0 bit3 0 bit2 PWD bit1 INTR bit0 0 Note: initial value: 00H Rev. 2010 CompactFlash Card Name CHGED (CARD->) R/W R Function This bit indicates that CRDY-BSY bit on Pin Replacement register is set to "1". When CHGED bit is set to "1", -STSCHG pin is held "L" at the confition of SIGCHG bit set to "1" and the card configured for the I/O interface. This bit is set or reset by the host for enabling and disabling the status-change signal (-STSCHG pin). When the card is configured I/O card interface and this bit is set to "1", -STSCHG pin is controlled by CHGED bit. If this bit is set to "0", -STSCHG pin is kept "H". The host sets this field to "1" when it can provide I/O cycles only with on 8bit data bus (D7 to D0). When this bit is set to "1", the card enters sleep state (Power Down mode). When this bit is reset to "0", the card transfers to idle state (active mode). RRDY/-BSY bit on Pin Replacement Register becomes BUSY when this bit is changed. RRDY/-BSY will not become Ready until the power state requested has been entered. This card automatically powers down when it is idle, and powers back up when it receives a command. This bit state is available whether I/O card interface has been configured or not. This signal remains true until the condition which cased the interrupt request has been serviced. If interrupts are disabled by the ­IEN bit in the Device Control Register, this bit is a zero. SIGCHG (HOST->) IOIS8 (HOST->) R/W R/W PWD (HOST->) R/W INTR (CARD->) R 4. 3. 3 Pin Replacement register (Address 204H) This register is used for providing the signal state of ­IREQ signal when the card configured I/O card interface. bit7 0 Note: initial value: 00H bit6 0 bit5 CRDY/-BSY bit4 0 bit3 1 bit2 1 bit1 RRDY/-BSY bit0 0 Name CRDY/-BSY (HOST->) RRDY/-BSY (HOST->) R/W R/W Function This bit is set to "1" when the RRDY/-BSY bit changes state. When written, this bit is used for CRDY/-Bsy bit masking. R/W 4. 3. 4 Socket and Copy register (Address 206H) This register is used for identification of the card from the other card. This register should be set by host before this card's Configuration Option register set. bit7 0 Note: initial value: 00H bit6 0 bit5 0 bit4 DRV# bit3 0 bit2 0 bit1 0 bit0 0 Name DRV# (HOST->) R/W Function These fields are used for the configuration of the plural cards. [. . . ] In PCMCIA mode this value shall be 0h Recommended Multiword DMA transfer cycle time . In PCMCIA mode this value shall be 0h Minimum PIO transfer cycle time without flow control Minimum PIO transfer cycle time with IORDY flow control Reserved Major version number Minor version number Command sets supported 0 Command sets supported 1 Command sets supported 2 Command sets Enable 0 Command sets Enable 1 Command sets Enable 2 Ultra DMA support and selected Time required for Security erase unit completion Time required for Enhanced security erase unit completion Current Advanced power management value Reserved Rev. 2010 CompactFlash Card Word address 93 - 127 128 129-159 160 161 162 163 164 165-175 176-255 Default value 0000H 0000H 0000H 81F4H 0000H 0000H 0092H 891BH 0000H 0000H Bytes 2 2 64 2 2 2 2 2 22 140 Reserved Security status Data field type information Vendor unique bytes Power requirement description Reserved Key management schemes supported CF Advanced True lDE Timing Mode Capability and Setting *CF Advanced PCMCIA I/O and Memory Timing Mode Capability and Setting Reserved Reserved 6. Electrical specification 6. 1 Absolute Ratings Symbol VDD VIN IIN TSTG Parameter Supply voltage Input Voltage DC Input Current Storage temperature Ratings - 0. 3 to +7. 0 -0. 3 to VDD +0. 3 -10 -40 to +85 Units V V mA Industrial 6. 2 Recommand operating conditions Symbol VDD Ta Parameter DC supply voltage Operating temperature 5V 3. 3V Industrial Ratings 4. 5 to +5. 5 3. 0 to +3. 6 0 to +70 Units V V 6. 3 DC Characteristics 1( Ta=-40 to +85 , Vcc = 3. 3V +/- 5%) Symbol Vcc Parameter Supply Voltage Conditions MIN 2. 97 MAX 3. 63 Unix V V V Non- Schmitt trigger VIH High level inpup voltage Schmitt trigger Non- Schmitt trigger VIL Low level input voltage Schmitt trigger VOH VOL High level output voltage Low level output voltage 2. 4 2. 05 0. 6 1. 25 Vcc-0. 8 0. 8 V V V V Rev. [. . . ]