User manual MAXTOR CFA1080A

[. . . ] CFA810A/CFA1080A Intelligent Disk Drive Product Manual Production Release Per EC 5687 P/N 00550-001 Revision A May 1994 3081 Zanker Road San Jose, CA 95134-2128 (408) 456-4500 FCC Notice This equipment generates and uses radio frequency energy and, if not installed and used properly; that is, in strict accordance with the manufacturer's instructions, may cause interference to radio and television reception. It has been designed to provide reasonable protection against such interference in a residential installation. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause interference to radio or television reception, which can be determined by turning the equipment on and off, you are encouraged to try to correct the interference by one or more of the following measures: · · · Reorient the receiving antenna. [. . . ] This bit will be reset at power-up and will remain reset until the drive is up to speed and ready to accept a command. DRQ is the data request bit, which indicates that the drive is ready for transfer of a word or a byte of data between the host and the Data register. CORR is the corrected data bit, which is set: - - when a correctable data error has been encountered and the data has been corrected on a read verify if any sector was corrected the bit is valid · · · This condition will not terminate either a Multi-Sector Read or a Read Multiple command. · · IDX is the index bit which is set once per disk revolution. ERR is the error bit, which indicates that the previous command ended in some type of error. The other bits in the Status register, as well as the bits in the Error register, will have additional information as to the cause of the error. Alternate Status Register Port Address: Chip Select: Register Address: Function: 3F6 -HOST CS1 6 Read only Description: This register contains the same information as the Status register in the Task File. The only difference is that reading this register does not imply interrupt acknowledge to reset a pending interrupt. The bits in this register are defined below: Bit 7 BSY Bit 6 DRDY Bit 5 DWF Bit 4 DSC Bit 3 DRQ Bit 2 CORR Bit 1 IDX Bit 0 ERR See the description of the Status register for definitions of the bits in this register. Page 46 Filepro CFA810A/CFA1080A Register Addresses and Functions Chapter 6 Digital Output Register Port Address: Chip Select: Register Address: Function: 3F6 -HOST CS1 6 Write only Description: This register contains two control bits as follows: Bit 7 not used where: · Bit 6 not used Bit 5 not used Bit 4 not used Bit 3 not used Bit 2 SRST Bit 1 -IEN Bit 0 not used SRST is the host software reset bit. The drive is held reset when this bit is active, and enabled when this bit is inactive. - - When this bit is active (=0) and the drive is selected, the host interrupt, +IRQ, is enabled through a tri-state buffer to the host. When this bit is inactive (=1), or the drive is not selected, the +IRQ pin will be in a high impedance state, regardless of the presence or absence of a pending interrupt. · Technical Reference Manual Page 47 Chapter 6 Register Addresses and Functions Drive Address Register Port Address: Chip Select: Register Address: Function: 3F7 -HOST CS1 7 Read only Description: This register loops back the drive select and head select addresses of the currently selected drive. The bits in this register are as follows: Bit 7 RSVD where: · Bit 6 -WTG Bit 5 -HS3 Bit 4 -HS2 Bit 3 -HS1 Bit 2 -HS0 Bit 1 -DS1 Bit 0 -DS0 RSVD is reserved and negated by the drive. When the host reads the drive address register, this bit must be in a high impedance state. -WTG is the write gate bit, which is active when writing to the disk drive is in progress. -HS3 through -HS0 are the one's complement of the binary coded address of the currently-selected head. For example, if -HS3 through -HS0 are 1 1 0 0, respectively, head 3 is selected. -DS1 is the drive select bit for drive 1, and should be active when drive 1 is selected and active. -DS0 is the drive select bit for drive 0, and should be active when drive 0 is selected and active. Note: Bit 7 is not driven for compatibility with the floppy drive address space. If your system is different, you may have to drive this bit when this register is read. · · · · Command Register Port Address: Chip Select: Register Address: Function: 1F7 -HOST CS0 7 Write only Description: The eight-bit code written to this register passes the command from the host to the drive. Refer to chapter 7 for a list of executable commands with the command codes and necessary parameters for each command. Page 48 Filepro CFA810A/CFA1080A Register Addresses and Functions Chapter 6 This I/O map defines the register addresses and functions for these I/O locations. For ease of reference, the commands are listed in alphabetical order. Command Code b5 b4 b3 b2 0 0 0 1 0 1 1 0 0 1 1 0 0 1 1 0 1 0 0 1 1 1 1 1 0 1 1 0 0 0 0 0 0 1 1 0 0 1 0 0 1 0 1 0 x 1 0 0 0 1 0 0 0 0 x x 1 0 0 1 0 0 1 0 0 x 1 0 0 p 0 1 0 1 0 x x 1 1 0 0 1 0 0 Command: Conner Specific Execute Drive Diagnostic Format Track Identify Drive Init. Drive Parameters Physical Seek Power Commands Read DMA Read Multiple Read Sector(s) Read Sector Buffer Read Verify Sector(s) Recalibrate Seek Set Features Set Multiple Mode Translate Write DMA Write Multiple Write Sectors Write Sector Buffer b7 1 1 0 1 1 1 1 1 1 0 1 0 0 0 1 1 1 1 1 0 1 b6 0 0 1 1 0 1 1 1 1 0 1 1 0 1 1 1 1 1 1 0 1 b1 1 0 x 0 0 1 p 0 0 L 0 0 x x 1 1 0 1 0 L 0 b0 0 0 x 0 1 0 p r 0 r 0 r x x 1 0 1 r 1 r 0 SC y n n n y y y y y y e y n n y y n y y y e Parameters: SN CY SDH y n n n n y n y y y n y n n n n y y y y n y n y n n y n y y y e y n y n n y y y y e d d y d y y d y y y d y d y d d y y y y d PR n n n n n y n n n n n n n n y n y n n n n where: · L is the long bit, if 1, R/W Long commands are executed, if 0, normal R/W commands are performed. [. . . ] DRQ is reset and BSY is set immediately when the host fills the sector buffer. If no error is detected, the cylinder, head, and sector registers are updated to point at the next sequential sector. If an error occurs during a multiple sector write, it will terminate at the sector where the error occurs. The Task File indicates the location of the sector where the error occurred. [. . . ]