User manual LON EN29F040A

[. . . ] EN29F040A EN29F040A 4 Megabit (512K x 8-bit) Flash Memory FEATURES · 5. 0V operation for read/write/erase operations · Fast Read Access Time - 45ns, 55ns, 70ns, and 90ns · Sector Architecture: 8 uniform sectors of 64Kbytes each Supports full chip erase Individual sector erase supported Sector protection: Hardware locking of sectors to prevent program or erase operations within individual sectors High performance program/erase speed Byte program time: 10µs typical Sector erase time: 500ms typical Chip erase time: 3. 5s typical · JEDEC Standard program and erase commands · JEDEC standard DATA polling and toggle bits feature · Single Sector and Chip Erase · Sector Unprotect Mode · Embedded Erase and Program Algorithms · Erase Suspend / Resume modes: Read and program another Sector during Erase Suspend Mode · 0. 23 µm triple-metal double-poly triple-well CMOS Flash Technology · Low Vcc write inhibit < 3. 2V · 100K endurance cycle · Package Options - 32-pin PDIP - 32-pin PLCC - 32-pin TSOP (Type 1) · Commercial and Industrial Temperature Ranges · - · Low Standby Current - 1µA CMOS standby current-typical - 1mA TTL standby current · Low Power Active Current - 30mA active read current - 30mA program/erase current GENERAL DESCRIPTION The EN29F040A is a 4-Megabit, electrically erasable, read/write non-volatile flash memory. Organized into 512K words with 8 bits per word, the 4M of memory is arranged in eight uniform sectors of 64Kbytes each. The EN29F040A features 5. 0V voltage read and write operation, with access times as fast as 45ns to eliminate the need for WAIT states in high-performance microprocessor systems. The EN29F040A has separate Output Enable ( OE ), Chip Enable ( CE ), and Write Enable ( W E ) controls, which eliminate bus contention issues. [. . . ] The hardware sector unprotection feature re-enables both program and erase operations in previously protected sectors. Sector protection/unprotection must be implemented using programming equipment. The procedure requires a high voltage (VID) on address pin A9 and the control pins. for an additional supplement on this feature. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 10 ©2003 Eon Silicon Solution, Inc. , www. essi. com. tw Rev. B, Issue Date: 2004/04/01 EN29F040A WRITE OPERATION STATUS DQ7 DATA Polling The EN29F040A provides DATA Polling on DQ7 to indicate to the host system the status of the embedded operations. The DATA Polling feature is active during the Byte Programming, Sector Erase, Chip Erase, and Erase Suspend. (See Table 6) When the Byte Programming is in progress, an attempt to read the device will produce the complement of the data last written to DQ7. Upon the completion of the Byte Programming, an attempt to read the device will produce the true data last written to DQ7. For the Byte Programming, DATA polling is valid after the rising edge of the fourth WE or CE pulse in the four-cycle sequence. When the embedded Erase is in progress, an attempt to read the device will produce a "0" at the DQ7 output. Upon the completion of the embedded Erase, the device will produce the "1" at the DQ7 output during the read. For Chip Erase, the DATA polling is valid after the rising edge of the sixth W E or CE pulse in the six-cycle sequence. For Sector Erase, DATA polling is valid after the last rising edge of the sector erase W E or C E pulse. DATA Polling must be performed at any address within a sector that is being programmed or erased and not a protected sector. Otherwise, DATA polling may give an inaccurate result if the address used is in a protected sector. Just prior to the completion of the embedded operations, DQ7 may change asynchronously when the output enable ( OE ) is low. This means that the device is driving status information on DQ7 at one instant of time and valid data at the next instant of time. Depending on when the system samples the DQ7 output, it may read the status of valid data. Even if the device has completed the embedded operations and DQ7 has a valid data, the data output on DQ0-DQ6 may be still invalid. The valid data on DQ0-DQ7 will be read on the subsequent read attempts. The DATA Polling (DQ7) timing diagram is shown in Figure 8. DQ6 Toggle Bit I The EN29F040A provides a "Toggle Bit" on DQ6 to indicate to the host system the status of the embedded programming and erase operations. (See Table 6) During an embedded Program or Erase operation, successive attempts to read data from the device at any address (by toggling OE or CE ) will result in DQ6 toggling between "zero" and "one". Once the embedded Program or Erase operation is complete, DQ6 will stop toggling and valid data will be read on the next successive attempts. During Byte Programming, the Toggle Bit is valid after the rising edge of the fourth WE pulse in the four-cycle sequence. [. . . ] AC CHARACTERISTICS Write (Erase/Program) Operations Parameter Symbols JEDEC Standard Description Write Cycle Time Address Setup Time Address Hold Time Data Setup Time Data Hold Time Output Enable Setup Time Output Enable Hold Time Read Toggle and DATA Polling Min Min Min Min Min Min MIn Min Min Min Min Min Min Typ Programming Operation Max Typ Sector Erase Operation Max Typ Chip Erase Operation Vcc Setup Time Rise Time to VID Max Min Min -45 45 0 35 20 0 0 0 10 0 0 0 25 20 7 200 0. 3 5 3 35 50 500 Speed Options -55 55 0 45 25 0 0 0 10 0 0 0 30 20 7 200 0. 3 5 3 35 50 500 -70 70 0 45 30 0 0 0 10 0 0 0 35 20 7 200 0. 3 5 3 35 50 500 -90 90 0 45 45 0 0 0 10 0 0 0 45 20 7 200 0. 3 5 3 35 50 500 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns µs µs s s s s µs ns tAVAV tAVWL tWLAX tDVWH tWHDX tWC tAS tAH tDS tDH tOES tOEH tGHWL tELWL tWHEH tWLWH tWHDL tWHWH1 tWHWH2 tWHWH3 tGHWL tCS tCH tWP tWPH tWHWH1 tWHWH2 tWHWH3 tVCS tVIDR Read Recovery Time before Write ( OE High to W E Low) CE SetupTime CE Hold Time Write Pulse Width Write Pulse Width High This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 23 ©2003 Eon Silicon Solution, Inc. , www. essi. com. tw Rev. AC CHARACTERISTICS Write (Erase/Program) Operations Alternate CE Controlled Writes Parameter Symbols JEDEC Standard Description Write Cycle Time Address Setup Time Address Hold Time Data Setup Time Data Hold Time Output Enable Setup Time Output Read Enable Toggle and Hold Time Data Polling Read Recovery Time before Write ( OE High to CE Low) W E SetupTime W E Hold Time Speed Options -45 Min Min Min Min Min Min 0 10 Min Min Min Min Min Typ Programming Operation Max Typ Sector Erase Operation Max Typ Chip Erase Operation Vcc Setup Time Rise Time to VID Max Min Min 45 0 35 20 0 0 0 10 0 0 0 25 20 7 200 0. 3 5 3 35 50 500 -55 55 0 45 25 0 0 0 10 0 0 0 30 20 7 200 0. 3 5 3 35 50 500 -70 70 0 45 30 0 0 0 10 0 0 0 35 20 7 200 0. 3 5 3 35 50 500 -90 90 0 45 45 0 0 0 10 0 0 0 45 20 7 200 0. 3 5 3 35 50 500 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns µs µs s s s s µs ns tAVAV tAVEL tELAX tDVEH tEHDX tWC tAS tAH tDS tDH tOES tOEH tGHEL tWLEL tEHWH tELEH tEHEL tWHWH 1 tGHEL tWS tWH tCP tCPH tWHWH1 tWHWH2 tWHWH3 tVCS tVIDR Write Pulse Width Write Pulse Width High tWHWH 2 tWHWH 3 This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 24 ©2003 Eon Silicon Solution, Inc. , www. essi. com. tw Rev. ERASE AND PROGRAMMING PERFORMANCE Parameter Sector Erase Time Chip Erase Time Byte Programming Time Chip Programming Time Erase/Program Endurance Typ 0. 3 3 7 2 100K Limits Max 5 35 200 5 Unit sec sec µs Excludes system level overhead sec cycles Minimum 100K cycles guaranteed Comments Excludes 00H programming prior to erasure Table 12. LATCH UP CHARACTERISTICS Parameter Description Input voltage with respect to Vss on all pins except I/O pins (including A9 and OE ) Input voltage with respect to Vss on all I/O Pins Vcc Current Min -1. 0 V -1. 0 V -100 mA Max 12. 0 V Vcc + 1. 0 V 100 mA Note : These are latch up characteristics and the device should never be put under these conditions. [. . . ]