User manual JETWAY V333DAR1C

[. . . ] V333DA AMD Socket A Athlon/Duron sG oGG G03-V333DAR1C 2002 ~ 3 Ӽ: Athlon M Duron O ]tb 󤧳W tӪ աC AMD qUӼСCLӼФΦW٬ݨ qҦC ƶȬϥθTѡA-קNtq A åB ϥΪ̻ UT ѨM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 V333DA DO² DOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . [. . . ] OS Select For DRAM > 64MB Allows OS2 to be used with >64MB or DRAM. Set to OS/2 if using more than 64MB and running OS/2. 3-6 Advanced Chipset Features The Advanced Chipset Features Setup option is used to change the values of the chipset registers. These registers control most of the system options in the computer. 27 CMOS Setup Utility Copyright(C) 1984-2001 Award Software Advanced Chipset Features > DRAM Timing Settings > AGP Timing Settings > PCI Timing Settings System BIOS Cacheable Video RAM Cacheable Memory Hole Press Enter Press Enter Press Enter Disabled Disabled Disabled Item Help Menu Level > Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit F5:Previous Values F6:Optimized Defaults F1:General Help F7:Standard Defaults DRAM Timing Settings Please refer to section 3-6-1 AGP Timing Settings Please refer to section 3-6-2 PCI Timing Settings Please refer to section 3-6-3 System BIOS Cacheable Selecting Enabled allows caching of the system BIOS ROM at F0000h-FFFFFh, resulting in better system performance. However, if any program writes to this memory area, a system error may result. Video RAM Cacheable Select Enabled allows caching of the video BIOS, resulting in better system performance. However, if any program writes to this memory area, a system error may result. Memory Hole You can reserve this area of system memory for ISA adapter ROM. The user information of peripherals that need to use this area of system memory usually discusses their memory requirements. The settings are: Enabled and Disabled. 3-6-1 DRAM Timing Settings CMOS Setup Utility Copyright(C) 1984-2001 Award Software DRAM Timing Settings 28 Auto Configuration RAS Active Time RAS Precharge Time RAS to CAS Delay CAS Latency Bank Interleave DRAM Command Rate Optimized 6T 3T 3T 2. 5T 4 Bank 2T Command Item Help Menu Level >> Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit F1:General Help F5:Previous Values F6:Optimized Defaults F7:Standard Defaults RAS Active Time This field let's you insert a timing delay between the CAS and RAS strobe signals, used when DRAM is written to, read from, or refreshed. Fast gives faster performance; and Slow gives more stable performance. This field applies only when synchronous DRAM is installed in the system. RAS Precharge Time If an insufficient number of cycles is allowed for the RAS to accumulate its charge before DRAM refresh, the refresh may be incomplete and the DRAM may fail to retain date. Fast gives faster performance; and Slow gives more stable performance. This field applies only when synchronous DRAM is installed in the system. CAS Latency When synchronous DRAM is installed, the number of clock cycles of CAS latency depends on the DRAM timing. The settings are: 2T and 2. 5T. 3-6-2 AGP Timing Settings CMOS Setup Utility Copyright(C) 1984-2001 Award Software AGP Timing Settings AGP AGP AGP AGP AGP AGP AGP CPU AGP Transfer Aperture Size Mode Driving Control Driving Value Fast Write Master 1 WS Write Master 1 WS Read to AGP Post Write Delay Transaction 64M Auto Auto DA Disabled Enabled Enabled Disabled Disabled Item Help Menu Level >> Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit F1:General Help F5:Previous Values F6:Optimized Defaults F7:Standard Defaults Note: Change these settings only if you are familiar with the chipset. 3-6-3 PCI Timing Settings CMOS Setup Utility Copyright(C) 1984-2001 Award Software PCI Timing Settings 29 PCI PCI CPU PCI Master 1 WS Write Master 1 WS Read to AGP Post Write Delay Transaction Disabled Disabled Disabled Disabled Item Help Menu Level >> Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit F5:Previous Values F6:Optimized Defaults F1:General Help F7:Standard Defaults PCI Delay Transaction The chipset has an embedded 32-bit posted write buffer to support delay transactions cycles. Select Enabled to support compliance with PCI specification version 2. 1. The settings are: Enabled and Disabled. 3-7 Integrated Peripherals CMOS Setup Utility Copyright(C) 1984-2001 Award Software Integrated Peripherals > OnChip IDE Function > OnChip Device Function > Onboard Super IO Function Init Display First Press Enter Press Enter Press Enter PCI Slot Item Help Menu Level > Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit F1:General Help F5:Previous Values F6:Optimized Defaults F7:Standard Defaults OnChip IDE Function Please refer to section 3-7-1 OnChip Device Function Please refer to section 3-7-2 Onboard Super IO Function Please refer to section 3-7-3 Init Display First This item allows you to decide to activate whether PCI Slot or AGP VGA first. The settings are: PCI Slot, AGP Slot. 3-7-1 OnChip IDE Function CMOS Setup Utility Copyright(C) 1984-2001 Award Software OnChip IDE Function 30 OnChip IDE Channel0 OnChip IDE Channel1 Primary Master PIO Primary Slave PIO Secondary Master PIO Secondary Slave PIO Primary Master UDMA Primary Slave UDMA Secondary Master UDMA Secondary Slave UDMA IDE 32-bit Transfer Mode IDE HDD Block Mode IDE Prefetch Mode Delay For HDD (Secs) Enabled Enabled Auto Auto Auto Auto Auto Auto Auto Auto Enabled Enabled Enabled 0 Item Help Menu Level >> Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit F1:General Help F5:Previous Values F6:Optimized Defaults F7:Standard Defaults OnChip IDE Channal0/Channel1 The integrated peripheral controller contains an IDE interface with support for two IDE channels. Primary/Secondary Master/Slave PIO The four IDE PIO (Programmed Input/Output) fields let you set a PIO mode (0-4) for each of the four IDE devices that the onboard IDE interface supports. In Auto mode, the system automatically determines the best mode for each device. Primary/Secondary Master/Slave UDMA Ultra DMA/33 implementation is possible only if your IDE hard drive supports it and the operating environment includes a DMA driver (Windows 95 OSR2 or a third-party IDE bus master driver). [. . . ] ENTER PASSWORD: Type the password, up to eight characters in length, and press <Enter>. The password typed now will clear any previously entered password from CMOS memory. You may also press <Esc> to abort the selection and not enter a password. To disable a password, just press <Enter> when you are prompted to enter the password. [. . . ]