User manual JETWAY 615TCFR1C

[. . . ] 615TCF/615TCS Socket 370 sG oG G03-615CFR1C 2001 ~ 7 Ӽ: Pentium M MMX O Intel qUӼСCLӼФΦW٬ݨ qҦC ϥΪ̻ UT ѨM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 DO² Ĥ@ 1-1 DOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . [. . . ] During Disabled, A deferrable CPU cycle will be Deferred immediately after the GMCH receives another ADS#. Delayed Transaction The chipset has an embedded 32-bit posted write buffer to support delay transactions cycles. Select Enabled to support compliance with PCI specification version 2. 1. The settings are: Enabled and Disabled. 31 On-Chip Video Window Size This option enabled/disabled the on-chip video windows size for VGA driver use. AGP Graphics Aperture Size This option determines the effective size of the graphics aperture used in the particular PAC configuration. The AGP aperture is memory-mapped, while graphics data structure can reside in a graphics aperture. The aperture range should be programmed as not cacheable in the processor cache, accesses with the aperture range are forwarded to the main memory, then PAC will translate the original issued address via a translation table that is maintained on the main memory. The option allows the selection of an aperture size of 32MB, 64MB. 3-6-1 SDRAM Timing Setting CMOS Setup Utility Copyright(C) 1984-2000 Award Software SDRAM Timing Setting SDRAM CAS Latency Time SDRAM Cycle Time Tras/Trc SDRAM RAS-to-CAS Delay SDRAM RAS Precharge Time DRAM CTL Buffer strengths DRAM MD Buffer strengths 3 6/8 3 3 Normal Normal Item Help Menu Level >> When set to "Auto", BIOS will program this Timing mainly by the SPD method. SPD means "Serial Presence Detect", which enables the BIOS to access the manufacturer settings stored in DRAM module. Move Enter:Select Item +/-/PU/PD:Value F10:Save ESC:Exit F1:General Help F5:Previous Values F6:Optimized Defaults F7:Standard Defaults SDRAM CAS Latency Time When synchronous DRAM is installed, the number of clock cycles of CAS latency depends on the DRAM timing. SDRAM Cycle Time Tras/Trc Select the number of SCLKs for an access cycle. SDRAM RAS-to-CAS Delay 32 This field let's you insert a timing delay between the CAS and RAS strobe signals, used when DRAM is written to, read from, or refreshed. Fast gives faster performance; and Slow gives more stable performance. This field applies only when synchronous DRAM is installed in the system. SDRAM RAS Precharge Time If an insufficient number of cycles is allowed for the RAS to accumulate its charge before DRAM refresh, the refresh may be incomplete and the DRAM may fail to retain date. Fast gives faster performance; and Slow gives more stable performance. This field applies only when synchronous DRAM is installed in the system. The settings are: 2 and 3. 3-7 Integrated Peripherals CMOS Setup Utility Copyright(C) 1984-2000 Award Software Integrated Peripherals On-Chip IDE Function On-Chip SIO Function On-Chip Device Function Init Display First Power On Function KB Power ON Password Hot Key Power ON POWER After PWR-fail Press Enter Press Enter Press Enter PCI Slot BUTTON ONLY Enter Ctrl-F1 off Item Help Menu Level > Move Enter:Select Item +/-/PU/PD:Value F10:Save ESC:Exit F5:Previous Values F6:Optimized Defaults F1:General Help F7:Standard Defaults On-Chip IDE Function Please refer to section 3-7-1 On-Chip SIO Function Please refer to section 3-7-2 On-Chip Device Function Please refer to section 3-7-3 Init Display First This item allows you to decide to activate whether PCI Slot or on-chip VGA first. Power On Function 33 This function allows you to select the item to power on the system. The settings are: Button Only, Mouse Left, Mouse Right, Password, Hotkey, and keyboard 98. Power After PWR-Fail This option will determine how the system will power on after a power failure. 3-7-1 On-Chip IDE Function CMOS Setup Utility Copyright(C) 1984-2000 Award Software On-Chip IDE Function On-Chip Primary PCI IDE On-Chip Secondary PCI IDE IDE Primary Master PIO IDE Primary Slave PIO IDE Secondary Master PIO IDE Secondary Slave PIO IDE Primary Master UDMA IDE Primary Slave UDMA IDE Secondary Master UDMA IDE Secondary Slave UDMA IDE 32-bit Transfer Mode IDE HDD Block Mode Delay For HDD (Secs) Enabled Enabled Auto Auto Auto Auto Auto Auto Auto Auto Enabled Enabled 0 Item Help Menu Level >> Move Enter:Select Item +/-/PU/PD:Value F10:Save ESC:Exit F5:Previous Values F6:Optimized Defaults F1:General Help F7:Standard Defaults On-Chip Primary/Secondary PCI IDE The integrated peripheral controller contains an IDE interface with support for two IDE channels. IDE Primary/Secondary Master/Slave PIO The four IDE PIO (Programmed Input/Output) fields let you set a PIO mode (0-4) for each of the four IDE devices that the onboard IDE interface supports. In Auto mode, the system automatically determines the best mode for each device. [. . . ] You determine when the password is required within the BIOS Features Setup Menu and its Security option. If the Security option is set to "System", the password will be required both at boot and at entry to Setup. If set to "Setup", prompting only occurs when trying to enter Setup. Supervisor password: User password: ĥ| bDO]ˤ t@ MAGIC INSTALL ФCoiФ]tDOһݪ 42 ҦXʵ{M@ǧKO n ˵{nAɤާAiX ²Ʀw˨BJAӦw˵{nNOq}o BunCåBAoФ ]]t@-Ӧ۰ w ʵ{ wˡAHΦXʵ{-nwˡAq MAGIC INSTALLC WINDOWS 95/98/98SE/NT4. 0/2000 MAGIC INSTALL Ф JоAMNX{ ЫU ڪqMܥоAΪ̦b :\SETUP. EXE" (]Aо|O MAGIC INSTALL De-CpGSX{e-A " } l " ؿܡ G ) " M J b MAGIC INSTALL De- 1. [. . . ]