User manual GIGABYTE GA-6LXGL

[. . . ] 9 Product Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Installing the CPU and CPU Cooler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Installing the CPU. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Installing the CPU Cooler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Dual Channel Memory Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Installing a Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 1-3-1 1-3-2 1-4 Installing the Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1-4-1 1-4-2 1-5 1-6 2-1 2-2 Back Panel Connectors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . [. . . ] Default setting is Enabled. PCI Slot #1/2/3 I/O ROM Onboard LAN #1/#2/#3/#4 I/O ROM PCI Common Settings PCI Latency Timer VGA Palette Snoop Value to be programmed into PCI Latency Timer Register. Options available: 32 PCI Bus Clocks/64 PCI Bus Clocks/96 PCI Bus Clocks/128 PCI Bus Clocks/160 PCI Bus Clocks/192 PCI Bus Clocks/224 PCI Bus Clocks/248 PCI Bus Clocks/. Default setting is Disabled. BIOS Setup - 40 - PERR Generation When this item is set to enabled, PCI bus parity error (PERR) is generated and is routed to NMI. When this item is set to enabled, PCI bus system error (SERR) is generated and is routed to NMI. Press [Enter] for configuration of advanced items. SERR Generation PCI Express Settings - 41 - BIOS Setup 2-2-3-1 PCI Express Settings PCI Express Device Register Settings Relaxed Ordering Enable/DIsable PCI Express Device Relaxed Ordering feature. Wnen this feature is enabled, the system will allow device to use 8-bit Tag field as a requester. Set maximum playlooad for PCI Express Device or allow system BIOS to select the value. Options available: Auto/128 Bytes/256 Bytes/512 Bytes/1024 Bytes/2048 Bytes/4096 Bytes. Set maximum Read Reuest size for PCI Express Device or allow system BIOS to select the value. Options available: Auto/128 Bytes/256 Bytes/512 Bytes/1024 Bytes/2048 Bytes/4096 Bytes. Wnen this feature is enabled, the system will allow generation of Extended Synchronization patterns. When enabled, the processor prevents the execution of code in data-only memory pages. When disabled, the processor will not restrict code execution in any memory area. Select whether to enable the Intel Virtualization Technology function. VT allows a single platform to run multiple operating systems in independent partitions. Select whether to enable the speculative prefetch unit of the processor. Options available: Turbo Performance/Max Non-Turbo Performance/Max bettery/Max Performance. Conventional Intel SpeedStep Technology switches both voltage and frequency in tandem between high and low levels in response to processor load. Default setting is Enabled. Execute Disable Bit Intel Virtualization Technology Hardware Prefetcher Adjacent Cache Line Prefetch CPU AES Boot performance mode EIST (Enhanced Intel SpeedStep Technology) Turbo Mode Energy Performance When this item is enabled, tje processor will automatically ramp up the clock speed of 1-2 of its processing cores to improve its performance. When this item is disabled, the processor will not overclock any of its core. - 46 - BIOS Setup Platform power limit lock CPU C State The larger value in MSR_ENERGY_PERFORMANCE_BIAS register, CPU will save more power but lose more performance. Note: This register will be changed by OS too if OS support it like Windows 2008 or newer Linux. [. . . ] • The following five items appears and configurable when the Launch CSM is set to Enabled. • If the Launch CSM is set to Disabled, the following five items will not be able to support Legacy mode. Options available: Do not launch/UEFI only/Legacy only/Legacy first/UEFI first. Default setting is Do not launch. Boot option filter Launch PXE OpROM policy Launch Storage OpROM policy Launch Video OpROM policy Determines which devices system will boot to. [. . . ]