User manual FUJITSU MPG3204AT

[. . . ] MPG3xxxAT DISK DRIVES PRODUCT MANUAL C141-E110-03EN REVISION RECORD Edition 01 02 03 Date published July, 2000 Aug. , 2000 Oct. , 2000 As the result of evaluation · · · · · Specifications of positioning time (slow) were modified. (See Table 1. 1) Description of data buffer value in Figure 4. 2 were modified. Revised contents Specification No. : C141-E110-**EN The contents of this manual is subject to change without prior notice. Copyright 2000 FUJITSU LIMITED C141-E110-03EN i This page is intentionally left blank. PREFACE This manual describes the MPG3xxxAT series, a 3. 5-inch hard disk drive with a BUILT-IN controller that is compatible with the ATA interface. [. . . ] Enabling the automatic power-down function means that the device automatically enters the standby mode after a certain period of time. If any command is not issued while the timer is counting down, the device automatically enters the standby mode. If any command is issued while the timer is counting down, the timer is initialized and the command is executed. The timer restarts countdown after completion of the command execution. The period of timer count is set depending on the value of the Sector Count register as shown below. × × × Status information DV xx xx xx xx Error information xx Sector Count register value 0 1 to 240 [X'00'] [X'01' to X'F0'] Point of timer Disable of timer (Value ×5) seconds (Value ­ 240) ×30 minutes 21 minutes 8 hours 21 minutes 15 seconds 241 to 251 [X'F1' to X'FB'] 252 253 [X'FC'] [X'FD'] 254 to 255 [X'FE' to X'FF'] C141-E110-03EN 5 - 45 At command issuance (I/O registers setting contents) 1F7H(CM) 1F6H(DH) 1F5H(CH) 1F4H(CL) 1F3H(SN) 1F2H(SC) 1F1H(FR) × × × X'97' or X'E3' DV xx xx xx Period of timer xx xx At command completion (I/O registers contents to be read) 1F7H(ST) 1F6H(DH) 1F5H(CH) 1F4H(CL) 1F3H(SN) 1F2H(SC) 1F1H(ER) × × × Status information DV xx xx xx xx Error information xx (23) IDLE IMMEDIATE (X'95' or X'E1') Upon receipt of this command, the device sets the BSY bit of the Status register, and enters the idle mode. This command does not support the automatic power-down function. At command issuance (I/O registers setting contents) 1F7H(CM) 1F6H(DH) 1F5H(CH) 1F4H(CL) 1F3H(SN) 1F2H(SC) 1F1H(FR) × × × X'95' or X'E1' DV xx xx xx xx xx xx At command completion (I/O registers contents to be read) 1F7H(ST) 1F6H(DH) 1F5H(CH) 1F4H(CL) 1F3H(SN) 1F2H(SC) 1F1H(ER) × × × Status information DV xx xx xx xx Error information xx 5 - 46 C141-E110-03EN (24) STANDBY (X'96' or X'E2') Upon receipt of this command, the device sets the BSY bit of the Status register and enters the standby mode. The device generates an interrupt even if the device has not fully entered the standby mode. If the device has already spun down, the spin-down sequence is not implemented. If the contents of the Sector Count register is other than 0, the automatic power-down function is enabled and the timer starts countdown when the device returns to idle mode. When the timer value reaches 0 (passed a specified time), the device enters the standby mode. If the contents of the Sector Count register is 0, the automatic power-down function is disabled. Thus, when the command involving a seek such as the READ SECTOR(S) command is received, the device processes the command after driving the spindle motor. At command issuance (I/O registers setting contents) 1F7H(CM) 1F6H(DH) 1F5H(CH) 1F4H(CL) 1F3H(SN) 1F2H(SC) 1F1H(FR) × × × X'96' or X'E2' DV xx xx xx Period of timer xx xx At command completion (I/O registers contents to be read) 1F7H(ST) 1F6H(DH) 1F5H(CH) 1F4H(CL) 1F3H(SN) 1F2H(SC) 1F1H(ER) × × × Status information DV xx xx xx xx Error information xx (25) STANDBY IMMEDIATE (X'94' or X'E0') Upon receipt of this command, the device sets the BSY bit of the Status register and enters the standby mode. This command does not support the automatic power-down sequence. C141-E110-03EN 5 - 47 At command issuance (I/O registers setting contents) 1F7H(CM) 1F6H(DH) 1F5H(CH) 1F4H(CL) 1F3H(SN) 1F2H(SC) 1F1H(FR) × × × X'94' or X'E0' DV xx xx xx xx xx xx At command completion (I/O registers contents to be read) 1F7H(ST) 1F6H(DH) 1F5H(CH) 1F4H(CL) 1F3H(SN) 1F2H(SC) 1F1H(ER) × × × Status information DV xx xx xx xx Error information xx (26) SLEEP (X'99' or X'E6') This command is the only way to make the device enter the sleep mode. Upon receipt of this command, the device sets the BSY bit of the Status register and enters the sleep mode. The device generates an interrupt even if the device has not fully entered the sleep mode. In the sleep mode, the spindle motor is stopped and the ATA interface section is inactive. The only way to release the device from sleep mode is to execute a software or hardware reset. At command issuance (I/O registers setting contents) 1F7H(CM) 1F6H(DH) 1F5H(CH) 1F4H(CL) 1F3H(SN) 1F2H(SC) 1F1H(FR) × × × X'99' or X'E6' DV xx xx xx xx xx xx 5 - 48 C141-E110-03EN At command completion (I/O registers contents to be read) 1F7H(ST) 1F6H(DH) 1F5H(CH) 1F4H(CL) 1F3H(SN) 1F2H(SC) 1F1H(ER) × × × Status information DV xx xx xx xx Error information xx (27) CHECK POWER MODE (X'98' or X'E5') The host checks the power mode of the device with this command. The host system can confirm the power save mode of the device by analyzing the contents of the Sector Count and Sector registers. After that, the device clears the BSY bit and generates an interrupt. Power save mode · During moving to standby mode · Standby mode · During returning from the standby mode · Idle mode · Active mode Sector Count register X'00' X'80' X'FF' At command issuance (I/O registers setting contents) 1F7H(CM) 1F6H(DH) 1F5H(CH) 1F4H(CL) 1F3H(SN) 1F2H(SC) 1F1H(FR) × × × X'98' or X'E5' DV xx xx xx xx xx xx C141-E110-03EN 5 - 49 At command completion (I/O registers contents to be read) 1F7H(ST) 1F6H(DH) 1F5H(CH) 1F4H(CL) 1F3H(SN) 1F2H(SC) 1F1H(ER) × × × Status information DV xx xx xx X'00' or X'FF' Error information xx (28) SMART (X'B0) This command performs operations for device failure predictions according to a subcommand specified in the FR register. If the value specified in the FR register is supported, the Aborted Command error is posted. [. . . ] When the power of the drive is turned on after the power is turned off once, the status of the write cache function returns to the default state. The default state is "write cache enable", and can be disable by the SET FEATURES command. · · · WRITE SECTOR(S) WRITE MULTIPLE WRITE DMA IMPORTANT When the write cache function is enabled, the transferred data from the host by the WRITE SECTOR(S) is not completely written on the disk medium at the time that the interrupt of command complete is generated. When the unrecoverable error occurs during the write operation, the command execution is stopped. [. . . ]