User manual CADENCE DESIGN SYSTEMS VOLTAGESTORM POWER DATASHEET

[. . . ] VOLTAGESTORM POWER AND POWER RAIL VERIFICATION DATASHEET ENCOUNTER PLATFORM To release innovative products in narrow market windows, companies need to focus precious engineering resources on where they add the most value--differentiating their designs. The Cadence® Encounter® digital IC design platform offers a full spectrum of technologies for nanometer-scale SoC design, helping both logic design www. [. . . ] Employing parasitic extraction that is manufacturing aware, and using patented static and dynamic algorithms, VoltageStorm technology continues to deliver power estimation and power rail analysis functionality and automation that you can depend on to both analyze and optimize your power networks throughout the design flow. BENEFITS · Enables efficient creation of on-chip power networks - Power routing sizes - De-coupling capacitance size and location · Minimizes risk of power-related silicon failures - Outputs comprehensive static and dynamic IR drop reports - Enables IR drop-aware timing and SI noise analysis (requires Cadence Encounter Timing System or CeltIC® NDC) · Optimizes low-power designs - Reports on-chip power density - Allows tradeoff between de-coupling capacitance and leakage - Validates power-switch sizes and power-up time - Verifies impact of power-up rush current on surrounding logic · Delivers an efficient, hierarchical analysis solution - Uses power grid views to maximize accuracy, performance, and capacity - Accurately models IP, custom digital, analog, and mixed-signal blocks · Supported by major reference flows, ASIC and IP vendors, and IDMs - Recommended by TSMC 7. 0 Reference Flow - Recommended by Starc ZD 3. 0 Flow - Library power grid views available directly from ARM and TSMC PowerMeter . lib DEF DSPF SPEF Figure 1: Example VoltageStorm plots (from left to right: IR drop, current density, and recommended de-coupling capacitance) FEATURES VoltageStorm power and power rail verification provides a comprehensive solution for power analysis and contains the functionality to accurately address the requirements associated with multiple design styles, including SoC, low-power, ASIC, and custom digital designs. Employing a combination of static and dynamic analysis approaches, VoltageStorm solutions can be used for power rail verification during the complete physical design creation flow, from early power planning through signoff prior to tapeout. To enable this comprehensive support, the VoltageStorm solution contains the functionality to calculate static and dynamic power consumption plus the functionality to perform both static and dynamic power rail analysis. POWER-DRIVEN DESIGN REqUIREMENTS For design teams to manage power consumption effectively, they must understand the source of the power, typically either active power or leakage power. For design teams to create robust power networks, in addition to understanding the details of power consumption, they must understand how to optimize power rail routing and sizes and the size and location of power switches (low-power designs) and de-coupling capacitors. VoltageStorm technology contains all of the functionality required to help you with these power-driven design requirements. POWERMETER POWER ESTIMATION PowerMeter is the power estimation functionality within the hierarchical, cell-based VoltageStorm solution. PowerMeter allows you to calculate static power consumption and dynamic power Dynamic Power Static Power TWF SLEW SDC TFC/ VCD1 DSPF SPEF TWF SLEW SDC VCD2 PowerMeter Instance-based Static Current mA Instance-based Dynamic Current Waveform cell cell 1. Optional VCD input used to seed activity Figure 2: PowerMeter data flow and usage 2. VCD required for vector-based analysis or to seed vectorless analysis www. cadence. com VOLTAGESTORM transients for all instances within a design. Optional VCD vectors can be used to seed the activity for static or vectorless dynamic power calculation. VCD vectors can also be used to directly drive PowerMeter for vector-based dynamic power calculation. PowerMeter uses a proprietary activity propagation algorithm that enables comprehensive nodal activity to always be generated, driven by default activity or seeded by partial activity information supplied by the designer. VoltageStorm PE + DG Full-chip Analysis GDS/ DEF Boundary Voltages IP or Memory Power Grid View Library LibGen Block Powergrid Views Analog or AMS GDS IP or Memory Analog or AMS VoltageStorm PE + DG Transistor Dynamic VAVO Transistor Dynamic Cell-based Dynamic Cell-based Static VOLTAGESTORM PE VoltageStorm PE enables hierarchical static power estimation using PowerMeter and hierarchical static power rail analysis. A static approach to power rail verification helps you rapidly check that the power rails can supply the amount of power needed by the design, without creating high amounts of IR drop. Static analysis if often used for pre-tapeout signoff for process technologies at and above 130nm, where the amount of natural de-coupling capacitance diminishes the need for dynamic analysis. Static analysis is a necessary step prior to executing dynamic analysis, to ensure that the power rails are robust prior to finetuning with de-coupling capacitance-- incorrectly sized power routing cannot be fixed by adding de-coupling capacitance. Block-level Analysis DEF VoltageStorm DG VoltageStorm PE Figure 3: Hierarchical power rail analysis level-shifting logic, voltage clamp circuitry, and the use of power switches to minimize leakage. [. . . ] VoltageStorm technology calculates instance operating voltages during the timing (switching) windows associated with each instance, and provides this information to Encounter Timing System or CeltIC NDC, which calculate the impact of IR drop on delay- and SI-generated noise. SPECIFICATIONS SySTEM REqUIREMENTS Specific requirements are design dependent · 512MB (min) DRAM · 2GB (min) swap space · 50MB software disc space · 2GB per 1M gates design disc space For more information, email us at info@cadence. com or visit www. cadence. com PLATFORM/OS · Sun Solaris 8 or 9 (32-bit, 64-bit) · HP-UX 11. 0 (32-bit, 64-bit) · Opteron Linux RHEL 3. 0 (64-bit) · Red Hat Linux RHEL 2. 1 (32-bit) · BM AIX 5. 1 (32-bit, 64-bit) VoltageStorm PE + DG Power Consumption PowerMeter INTERFACE · OpenAccess 2. 2 Chip & Package Design Creation or OpenAccess Dynamic Instance -based Power PowerStorm De-cap ECO IR Drop & EM Dynamic Instance Operation Voltage Cadence QRC Extraction Encouter Timing System SI-based Timing Analysis Figure 5: Flow to analyze impact of IR drop on timing and SI noise Cadence Design Systems, Inc. Corporate Headquarters 2655 Seely Avenue San Jose, CA 95134 800. 746. 6223 / 408. 943. 1234 www. cadence. com © 2006 Cadence Design Systems, Inc. Cadence, CeltIC, Encounter, Virtuoso, and VoltageStorm are registered trademarks, and the Cadence logo and SoC Encounter are trademarks of Cadence Design Systems, Inc. [. . . ]