User manual CADENCE DESIGN SYSTEMS VIRTUOSO LAYOUT MIGRATE DATASHEET

[. . . ] V Ir Tu o So LAy o uT MI g r AT E Figure 1: All components of the Virtuoso platform work together to support fast, silicon-accurate differentiated custom silicon G0007A DATASHEET The vIRTUOSO cUSTOm deSIgn plaTfORm When design objectives dictate manipulating precise analog quantities--voltages, currents, charges, and continuous ratios of parameter values such as resistance and capacitance--companies turn to custom design. Full-custom design maximizes performance while minimizing area and power. [. . . ] Integrated within the Virtuoso platform, Virtuoso Layout Migrate provides hierarchical twodimensional optimization algorithms to achieve significantly higher quality of results (Qor) than traditional methods using near-linear shrinks. Virtuoso Layout Cadence 7105_Figure 2 All layout structure is preserved, including Migrate is also a cost-effective solution connectivity, properties, ports, paramcompared to a purely manual approach-- eters, Pcells, multi-part paths (MPPs), and saving both time and labor. This enables the layout preservation and parameterized cell (Pcell) generated by Virtuoso Layout Migrate to substitution capabilities enhance producbe linked with the schematic, rerouted tivity, while the menu-driven flow configuration environment makes the setup procedure straightforward and efficient. hierarchical gDS or Virtuoso data with a target process technology as input, and is returned an LVS/DrC-correct hierarchical gDS or Virtuoso layout. Abutment, alignment, and pitch matching are all handled implicitly with hierarchical optimization to improve ease of use and capacity on hierarchical and arrayed designs (see Figure 2). Hierarchy-aware migration and technology mapping of Pcell layout is also fully supported (see Figure 3). by the Virtuoso router, manually edited, or modified using other layout functions. optimal layout is achieved with native support for two-dimensional rules such as diagonal spacing, minimum area, 45° angles, common run, and end of line. Virtuoso Layout Migrate is a productionproven solution for advanced process geometries requiring special design rules, including preferred rules used for yield and performance improvements (see Figure 4). eaSY-TO-USe menU-dRIven SeTUp and flOW cOnfIgURaTIOn Virtuoso Layout Migrate includes an easy-to-use menu-driven setup and flow configuration system in the familiar BenefITS · rapid layout migration through support of all types of layout hierarchy--typically resulting in an order-of-magnitude productivity improvement Cadence 7105_Figure 3 over manual efforts · Two-dimensional compaction that produces high Qor as compared with other solutions using one-dimensional algorithms · Easy-to-use menu-driven setup and configuration, allowing new users to produce high-quality results within days of installation VIRTUOSO LAYOUT IMAGE Runtime = 10 min. 0. 18 hm Source Layout 90nm Pcell view of Layout Figure 2: Example of fast layout migration showing implicit handling of hierarchy and abutment · Support for complex design rules at 90 nanometers and beyond, targeted to improve yield and circuit performance · Efficient engineering change order (ECo) implementation feaTUReS faST hIeRaRchIcal and TWOdImenSIOnal cOmpacTIOn Virtuoso Layout Migrate has been architected from the ground up to handle hierarchy directly--to enable rapid migration of hierarchical layout such as memories, custom datapath blocks, and mixed-signal designs. The user provides Figure 3: Fast and accurate layout migration with Pcell preservation, with an example of the Pcell map file V Ir Tu o S o LAyou T MIgr ATE w w w. With this menu system, the user can configure, run, and evaluate the results. The configurations menu allows the user to define an optimization flow consisting of preprocess, optimization, and postprocess commands. [. . . ] This device-matching technology works hierarchically and supports mismatched netlist/layout hierarchies. Figure 4: Example of fast layout migration showing the ability to handle complex design rules Figure 5: Easy-to-use menu-driven setup and flow configuration system--the fast track to productivity SpecIfIcaTIOnS laYOUT pROceSS and deSIgn RUle mIgRaTIOn · Hierarchical two-dimensional optimization · Structure preservation including paths, MPPs, symbolics, connectivity, and properties · Pcell substitution to replace Pcells or update their parameters during migration · Menu-driven setup and flow configuration system · ECo support with Virtuoso Schematic Editor and netlist-based device sizes Figure 6: Technology files are easy to understand and write--this example shows how to implement a gate spacing rule www. cadence. com VI r Tuo So L Ayou T MIgr ATE · Interactive user control in the Virtuoso environment · Support for device-specific and netspecific design rules in advanced process geometry · Preferred rules for improving yield and performance in leading-edge processes OTheR acceleRaTed laYOUT pROdUcTS · Virtuoso Accelerated Layout: high-end custom block physical layout editor · Virtuoso Layout Editor: industry-standard custom block physical layout editor · Virtuoso Chip Editor: chip integration and finishing physical layout editor · Virtuoso Chip Assembly router: custom block and chip routing tool · Cadence customer support that keeps your design team productive ­ Cadence applications engineers provide technical assistance ­ SourceLink® online support gives you access to software updates, technical documentation, and more--24 hours a day, seven days a week deSIgn InpUTS · Cadence CDBA database · SKILL · STrEAM format · Virtuoso Schematic Editor · CDL and SPICE netlist format cadence SeRvIceS and SUppORT · Customer-focused solutions that increase roI, reduce risk, and achieve your design goals faster ­ Collaborative approach and design infrastructure--virtual teaming ­ Proven methodology and flow tuned to your design environment ­ Design and EDA implementation expertise · Product and flow training to fit your needs and preferred learning style ­ over 80 instructor-led courses-- certified instructors, real-world experience ­ More than 25 Internet Learning Series (iLS) online courses for more information email us at info@cadence. com or log on to www. cadence. com deSIgn OUTpUTS · Cadence CDBA database · STrEAM format plaTfORm/OS · Sun/Solaris · HP-uX · Linux ThIRd-paRTY SUppORT · SKILL-based tools and functions · Process design kits (please refer to the PDK datasheets for more information) cadence design Systems, Inc. 2655 Seely avenue San Jose, ca 95134 p:+1. 800. 746. 6223 (within US) +1. 408. 943. 1234 (outside US) www. cadence. com © 2007 cadence design Systems, Inc. cadence, Sourcelink, and virtuoso are registered trademarks and the cadence logo is a registered trademark of cadence design Systems, Inc. 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