User manual CADENCE DESIGN SYSTEMS VIRTUOSO DIGITAL IMPLEMENTATION DATASHEET

[. . . ] VIR T U O S O D I G I TA L IMP L E M E N TAT I O N DATASHEET VIRTUOSO DIGITAL IMPLEMENTATION Designed to complement Cadence® Virtuoso® Layout Suite, Virtuoso Digital Implementation enables capacitylimited* execution of the complete digital implementation solution from RTL-toGDSII. [. . . ] The Encounter Digital Implementation System uses extremely fast, integrated engines for digital block implementation. Both technologies are based on the industry-leading Encounter digital IC design platform, proven to produce high quality of silicon (Figure 1). *Virtuoso Digital Implementation enables an RTL-to-GDSII solution that is limited in capacity. Encounter RTL Compiler synthesis is limited to a final mapped instance count of 50k instances or 200k generic instances. Encounter Digital Implementation is limited to a capacity of 50k instances. Cadence® Virtuoso® Digital Implementation is a complete synthesis and place-and-route system. It enables small digital block implementation in the context of an advanced analogdriven methodology for mixed-signal designs. Virtuoso Digital Implementation automates synthesis and optimizes place-and-route, accelerating the mixed-signal design process and ensuring the highest quality of silicon. VIRTUOSO PLATFORM Virtuoso Spec-driven Environment Virtuoso Spectre Circuit Simulator Virtuoso UltraSim Full-chip Simulator Virtuoso XL Layout Editor Virtuoso Chip Assembly Router Assura Physical Verification LEF/DEF OpenAccess ENCOUNTER PLATFORM Encounter RTL Compiler SoC Encounter L · Encounter digital implementation · 2-layer to n-layer · Cost effective Figure 1: Virtuoso Digital Implementation Two Virtuoso Digital Implementation licenses can be combined ("stacked") to double the capacity limits. [. . . ] Cadence the Cadence logo, Encounter, First Encounter, NanoRoute, Verilog, Virtuoso, and VoltageStorm are registered trademarks and SoC Encounter is a trademark of Cadence Design Systems, Inc. [. . . ]