User manual CADENCE DESIGN SYSTEMS VIRTUOSO CHIP ASSEMBLY ROUTER DATASHEET

[. . . ] VIR T u oS o C H I P A S S E M B LY R ouT E R Figure 1: All components of the Virtuoso platform work together to support fast, silicon-accurate differentiated custom silicon G0007A DATASHEET The vIRTUOSO cUSTOm deSIgn plaTfORm When design objectives dictate manipulating precise analog quantities--voltages, currents, charges, and continuous ratios of parameter values such as resistance and capacitance--companies turn to custom design. Full-custom design maximizes performance while minimizing area and power. [. . . ] It supports both block authoring and chip authoring solutions for custom digital, mixedsignal, and analog designs at any level of the hierarchy. A ARE POWER PERFORMAN C E PARA SI TICS Design Specification Multi-Mode Simulation Accelerated Layout Silicon Analysis Chip Finishing Open Database Constraint Management PDKs Customer IP Mfg vIRTUOSO chIp aSSemBlY ROUTeR The Virtuoso Chip Assembly Router is a design constraint- and process rule-driven, interactive, and fully automatic shapebased gridless router that supports transistor, cell, block and chip-level routing for custom digital, mixed-signal, and analog designs at any level of the design hierarchy. The Virtuoso Chip Assembly Router is interoperable with both the Virtuoso custom design platform and the Cadence Encounter® digital IC design platform. A unique blend of interactive and automatic design constraint- and process rule-driven routing features are provided, simplifying the most complex interconnect issues and maximizing productivity. The Virtuoso Chip Assembly Router supports 90nm and above process technology rules and is available on openAccess. BenefITS · Increased productivity and design quality through the specification and adherence of complex constraint and process rules during interactive and automatic routing · Simplified routing process using advanced features such as interactive push and shove, multi-net/bus, power, shielding, differential pairs, length, and crosstalk (see Figure 2) · Intuitive, easy-to-use interface with menu, command, and `do' file use options · open and flexible interoperability with the Virtuoso Schematic Editor and Virtuoso XL Layout Editor to support dynamic cross-probing and editing (see Figure 3). Interoperability with the SoC EncounterTM system is also supported Figure 2: Interactive and automatic bus and power routing Figure 3: Real-time interoperability with the Virtuoso Schematic Editor and the Virtuoso XL Layout Editor to provide accurate and accelerated block and chip design V I R Tu o S o C H IP ASSEMBLY R ouTER w w w. c a d e n ce. com feaTUReS deSIgn cOnSTRaInT and pROceSS RUle-dRIven ROUTIng The Virtuoso Chip Assembly Router accelerates the design process by providing a comprehensive set of design constraints and process rules that are specified, managed, and obeyed in a hierarchical precedence order during interactive and automatic routing. Dynamic real-time checking is performed during interactive routing with a halo display and automatic enforcement of the rules (see Figure 4). Automatic routing rules are obeyed during routing with optional post-route checking of the entire design or selective areas of the design. Figure 4: Interactive routing uses connectivity-, constraint-, and design-rule­driven features with push and shove for fast and accurate editing advanced InTeRacTIve ROUTIng feaTUReS The Virtuoso Chip Assembly Router simplifies the routing process with advanced interactive and automatic routing features. Interactive routing provides push and shove routing that eliminates the need to move other adjacent routing obstructions. Multi-net/bus routing supports the routing of two or more nets to efficiently route large bus structures. [. . . ] It is also interoperable through LEF/DEF and the openAccess database. www. cadence. com Figure 5: Interactive/automatic routing for analog, mixed-signal, and custom digital designs at the device, cell, block, and top levels SpecIfIcaTIOnS InTeRacTIve and aUTOmaTIc ROUTIng · Variable width and spacing rules · Antennae rule checking and fixing · 90nm process rule support (via adjacency, width-based, proximity, and maximum width) · Advanced interactive routing with push and shove, automatic completion, and route-to-cursor · Automatic global, track, and detail routing · Congestion analysis and automatic channel sizing · Device-, cell-, block-, and top-level chip assembly routing support (see Figure 5) · ECo functions · Design and rule reporting · Automatic power routing (pin-to-trunk, cell row, block ring, I/o ring, and stripes/ mesh) · Pre-route pin checking to insure routability · Incremental design and selective net routing · Polygon editor · Topology editor · Automatic specialty routing support for shielding, differential pairs, and symmetry (see Figure 6) · Net length control including minimum, maximum, and matched · Multiple via, via array, and minimum area via support · Pin width matching and tapering · Manufacturing and yield enhancement post-processing VIR T uo So CHIP ASSEMBLY R ou TER deSIgn InpUTS · Cadence CDBA database · openAccess database · LEF/DEF format · STREAM format · EDIF cadence SeRvIceS and SUppORT · Customer-focused solutions that increase RoI, reduce risk, and achieve your design goals faster ­ Collaborative approach and design infrastructure--virtual teaming ­ Proven methodology and flow tuned to your design environment ­ Design and EDA implementation expertise · Product and flow training to fit your needs and preferred learning style ­ over 80 instructor-led courses--certified instructors, real world experience ­ More than 25 Internet Learning Series (iLS) online courses · Cadence customer support that keeps your design team productive ­ Cadence applications engineers provide technical assistance ­ SourceLink® online support gives you access to software updates, technical documentation, and more--24 hours a day, seven days a week deSIgn OUTpUTS · Cadence CDBA database · openAccess design data · DEF format · STREAM format for more information email us at info@cadence. com or log on to www. cadence. com plaTfORm/OS · Sun/Solaris · HP-uX · IBM AIX · Linux Figure 6: Analog, mixed-signal routing features--auto net shielding cadence design Systems, Inc. 2655 Seely avenue San Jose, ca 95134 p:+1. 800. 746. 6223 (within US) +1. 408. 943. 1234 (outside US) www. cadence. com © 2007 cadence design Systems, Inc. cadence, encounter, virtuoso, and Sourcelink are registered trademarks and the cadence logo and Soc encounter are trademarks of cadence design Systems, Inc. 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