User manual CADENCE DESIGN SYSTEMS SIP DIGITAL DESIGN DATASHEET

[. . . ] However, this also means it requires expert engineering talent in widely divergent fields, which, to date, has limited mainstream adoption. By streamlining the integration of multiple high-pin-count chips onto a single substrate through a concurrent connectivity driven co-design methodology, the Cadence SiP digital co-design technology allows companies to adopt what were once expert engineering SiP design capabilities for mainstream product development. Cadence SiP solutions seamlessly integrate into Cadence Encounter ® technology for die abstract co-design, Cadence Virtuoso® technology for RF module design, and Cadence Allegro® technology for package/ board co-design. (See Figure 1. ) A COMPLETE CONNECTIVITY DRIVEN CO-DESIGN SOLUTION The Cadence digital-driven SiP flow focuses on the design challenges of integrating multiple large high-pin-count chips onto a single substrate. [. . . ] By using its embedded integration with a third-party supplied3Dfieldsolverenginecombined with a SPICE-based signal integrity simulation environment, engineers can make tradeoffs to minimize cost while maximizing performance of the package module interconnect. To model and simulatecomplex3DSiPstructures, SiP Digital SI integrated S-Parameter support, and fast, high-capacity simulation (10, 000 bits in seconds) to provide a unique combination of fast and accurate multigigahertz interconnect analysis. BENEFITS · Providesahighlyintegratedphysical and electrical design and simulation environment · Pre-postrouteinterconnectanalysiswith graphical topology exploration enables rapid what-if performance tuning · IncludesaSPICE-basedsimulation engine and embedded integration with athird-partysupplied3Dfieldsolver · Enablesrapidevaluationofcostversus performance tradeoffs through its virtual prototyping environment · Reads/writesCadenceDigitalSiP Layout files · Ensuressufficientandefficientpower delivery network (PDN) design www. ca de nce . com C A D ENC E SiP D I G I TAL DESI G N 3 KEY FEATURES* *Reference the product capabilities grid at the end of this datasheet to see what features are applicable to what product. to build the physical SiP implementation. The SiP architect can then use the graphical, intuitive editing tools to construct and evaluate critical sections of the design. (See Figure 5. ) SYSTEM CONNECTIVITY MANAGER The System Connectivity Manager is the "cockpit" or "dashboard" of the SiP Digital Architect. It allows the project architect to rapidly author and/or capture the connectivity of the SiP, which includes importing IC die Verilog netlists for chips that comprise the SiP design and interfacing to the PCB footprint symbol of the completed SiP. Embedded LVS routines and ECO management capabilities ensure that the logical SiP definition matches the physical SiP implementation, including any ICs that are partitioned and co-designed as part of the SiP. (See Figure 2. ) Figure 3: Virtual System Interconnect Models I/O PLANNER The IC die abstract I/O planner provides the definition and optimization of codesign die bump matrix, I/O pad ring/array through connectivity assignment, I/O placement, and redistribution layer (RDL) routing. It can create either a die abstract from scratch, or load an abstract from the digital IC design team (LEF/DEF or OA), and then optimize it in the context of the SiP substrate as well as other IC die in the design. The I/O planner is based on Encounter technology, ensuring it is 100 percent compatible with the chip design team's IC tools and provides complete IC technology file compliance. (See Figure 4. ) Figure 5: Substrate Floorplanner 3D DIE STACK EDITOR Thediestackeditorprovidesa3D construction environment for assembling complex die stacks which can include spacers, interposers and die attach methods such as wirebond and flip chip. (See Figure 6. ) Figure 2: System Connectivity Manager VIRTUAL SYSTEM INTERCONNECT (VSIC) MODELS An integrated graphical and topological interconnect modeling and simulation capability provides the ability to create and explore the signal integrity (SI) performance of proposed system-level connectivity. Embedded simulation capability provides time and frequency domain interconnect simulation, including industry-standard S-Parameter models. The embedded integration with a thirdpartysuppliedfull3Dquasi-staticfield solver further provides the extraction and creation of detailed, accurate geometric IBIS, RLGC or S-Parameter models of complex3Dinterconnectstructures. (See Figure 3. ) Figure 6: 3D Die Stack Editor 3D DESIGN VIEWER TheCadence3DDesignViewerisafull, solidmodel3Dviewerand3Dwirebond DRC solution for complex IC package designs. It allows users to visualize and investigate an entire design, or a selected design subset, such as a die stack or complex via array. It also provides a common reference point for cross-team design reviews. (See Figure 7. ) Figure 4: I/O Planner SUBSTRATE FLOORPLANNER The floorplanner allows the physical prototyping and evaluation of various substrate-level SiP implementation concepts. It provides a full rules-driven, connectivity-based capability that ensures a correct-by-construction approach. [. . . ] True wireprofile support enables DFMdriven design using manufacturing verified wire loop data. An included Kulicke & Soffa verified loop profile library ensures that any wirebond patterns designed meet manufacturing signoff. Wirebond attached die flags and power/ground rings can be quickly created, edited, and optimized for multiple voltage supplies. [. . . ]