User manual CADENCE DESIGN SYSTEMS QRC EXTRACTION DATASHEET

[. . . ] CAD E N CE Q R C E XT R ACT I O N Multi corner / Statistical Distributed processing DATASHEET CadenCe QRC extRaCtion As advanced process geometries become more popular, parasitic extraction becomes a necessity not only during the validation phase but also during design implementation. Cadence QRC Extraction is an integrated extraction solution for design implementation and validation at 90nm and below. [. . . ] It can output distributed or lumped, and coupled or decoupled RC data. Integrated with Encounter technology (Figure 2), QRC Extraction allows designers to reduce design turnaround time dramatically by performing incremental extraction, and to reach timing closure faster by utilizing signoffaccurate extraction data for timing and noise optimization. chip performance and yield. Built on a foundation of patented algorithms and proprietary extraction technologies, QRC Extraction brings the physics of interconnect parasitics into the Virtuoso environment for designing, characterizing, and optimizing chip layouts. Seamless integration with Virtuoso technology enables designers to perform parasitic extraction, backannotation, cross-probing, re-simulation, and analysis within a single design environment for increased productivity. QRC Extraction provides silicon-accurate resistance (R) and capacitance (C) interconnect parasitic extraction for all process technologies for transistor-level designs including RF, analog, mixed signal, custom, and memory. It provides highly accurate parasitics of both dense and sparse layouts for circuit simulation and analysis. As shown in Figure 3, QRC Extraction integrates with Cadence layout-vs. -schematic verification technologies (Cadence Assura® LVS, Cadence Physical Verification System, Mentor Graphics Calibre) and simulation technologies (Virtuoso Spectre® Circuit Simulator, Virtuoso Spectre RF Simulation Option, Virtuoso UltraSim Full-Chip Simulator). tRanSiStoR-level extRaCtion An integral part of the silicon analysis function inside the Virtuoso custom design environment, QRC Extraction supplies the critical parasitic information for optimizing www. ca de nce . com CA D ENC E Q RC EXTRAC TI O N 2 MUlti-CoRneR extRaCtion In designs at 130nm and below, a nominal corner extraction and some added margin is no longer sufficient to accurately predict parasitic effects. For example, signal integrity issues can occur at strong, high-temperature conditions. Thus, designers are required to perform extraction at multiple corners, and the number of corners grows as the process geometryshrinks. QRCExtractioncan extract multiple corners at once while significantly reducing overall runtime. GDSII DFII OA Cadence Physical Verification Cadence QRC Extraction StatiStiCal extRaCtion QRC Extraction offers statistical capability to efficiently reduce overall extraction runtimes whileprovidingaccurateresults. Ittakesinto account random variations of parameters likewidth, thickness, dielectricheight, metal resistivity, dielectric constant, via resistance, and temperature. Statistical extraction can significantly reduce extraction runtimes, especially at advanced process nodes. Drawn Devices Substrate R and C RLCK DFII/OA DSPF SPEF diStRiBUted pRoCeSSing QRC Extraction offers a distributed processing capability to efficiently extract multimillion-gate chips. It partitions the extractiontaskintomultipleindependent tasksthatcanbeexecutedinparallel using multiple CPUs and/or machines. Distributed processing can significantly reduce extraction runtimes, especially during the final signoff stages. Virtuoso Simulation and Analysis Figure 3: Complete transistor-level RLCK extraction advanCed SUBStRate Modeling CapaBility RF designers need a tool that not only extracts parasitic inductance accurately, but also evaluates the impact of substrate parasitics on their designs. [. . . ] It also uses fab-certified technology to predict contours across the process window and to predict device and interconnect silicon electrical behavior. Intermediate Local Chip surface Oxide loss Dishing Erosion Total copper loss Within-chip variation Isolated Isolated Dense array thin-lines wide-lines thin-lines Dense array wide-lines Figure 6: CMP interconnect variation As drawn As fabricated Timing difference with and without litho effect What you design is NOT what you get! Figure 7: Litho-aware extraction www. ca de nce . com CA D ENC E Q RC EXTRAC TI O N 4 ConFigURationS Cadence QRC Extraction is available in L, XL, and GXL configurations for both Encounter and Virtuoso design environments. Cadence QRC Extraction Features Cell-level and transistor-level extraction Multi-corner extraction in a single run for faster runtimes Common technology file for consistent results across transistor and gate levels Supports IR and EM analysis for transistor-level and gate-level designs Distributed processing support over multiple CPUs Capacity over 300K (cell) instances Hierarchical transistor-level extraction for increased capacity Incremental extraction within the SoC EncounterTM System for faster turnaround Integrated field solver support for enhanced accuracy Support RF analysis with RLCK extraction including substrate extraction Advanced support for L and K inductance extraction Advancedprocesssupportfor65nmandbelow Sensitivity analysis for substrate noise propagation in AMS designs Statistical- or variation-aware extraction support for random process variation Interface to model-based CMP extraction for increased accuracy Interface to litho-aware extraction for enhanced accuracy and reliability Advanced IR/EM support for powerMos designs RLCK reduction to increase simulation speed and capacity L x x x x x XL x x x x x x x x x x x x GXL x x x x x x x x x x x x x x x x x x SpeCiFiCationS extRaCtion ModeS · Black-box, gray-box, orwhite-box · LumpedRonly, Conly, orRCfor all nets · CoupledCforallnets · Self(L)andmutual(K)inductance extraction · Fully-distributedRCandRLCKfor all nets · RLCKforselectednetsandCforthe rest, or vice versa · Hierarchicaltransistor-level RC extraction · Abilitytoexcludenets, suchaspower and ground nets · Criticalnetandcriticalpathextraction · Contactcapacitance · Metalfill · Localinterconnect · Si, SiGe, andSOItechnologies · Coppertechnologysupport(lithography effects, dishing and erosion support) FoRMat SUppoRt · Designinputformats:GDSII, LEF/DEF, DFII, OA · Designoutputformats:ExtractedView, DSPF, xDSPF, SPICE, SPEF, xSPEF ManUFaCtURing eFFeCtS and advanCed phySiCal Modeling · 130nmandbelowcopper, via, and wire-edge enlargement and optical effects · Conformal, planar, multiple, andlow-k dielectrics · Non-planarprocesses · Airgaps · Trapezoidalconductors platFoRMS SunSolaris(32-bit, 64-bit) Linux(32-bit, 64-bit) IBM AIX (32-bit) FoUndRy SUppoRt Cadence QRC Extraction process files: · Certifiedandsupportedbyleading merchant foundries · Flowtestedandqualifiedwithfoundry PDKs · Developmentservicesareavailable email us at: icinfo@cadence. com or visit: www. cadence. com © 2008 Cadence design Systems, inc. Cadence, assura, encounter, Spectre, virtuoso, and voltageStorm are registered trademarks and the Cadence logo and SoC encounter are trademarks of Cadence design Systems, inc. [. . . ]