User manual CADENCE DESIGN SYSTEMS INCISIVE XTREME SERIES DATASHEET

[. . . ] These products provide a versatile functional verification system for behavioral-, RTL-, and gate-level designs. The latest offerings, Xtreme III Desktop and Xtreme III System, are both fourth-generation server-class hardware verification platforms. The Xtreme series of accelerators/emulators allows designers to create or modify existing architectures much quicker and earlier in their design flows. [. . . ] For library cells, the Xtreme library compiler automatically generates the appropriate mapping. For embedded-design memory blocks, a large internal cache and onboard memories are configured to the specific memory type. For complete system verification, large external memories are integrated using an extended memory board or workstation memory. 2 I N C I S I V E X T R E ME SERIES OF ACCELERATORS/EMULATORS w w w. c a d e n ce. com DEBUG IN SOFTWARELIKE ENVIRONMENT WHILE ACCELERATING The ability of Xtreme accelerators/emula tors to swap states between the software simulator and the RCC engine--in real time--makes them unique among hardware verification systems. During simulation, you can swap the state of the RCC engine into the software simulator to interactively debug the design and continue with software simulation. When your circuit is fully debugged and the problem isolated, you can swap the simulation state value back into the RCC engine for maximum performance. Xtreme III System extends these capabilities with in-circuit emulation. Xtreme behavioral processors provide a practical method for emulating non-synthesizable behavioral objects. A unique behavioral emulation capability maintains the performance level of emulation without sacrificing the flexibility of a software simulation environment. Behavioral constructs are event-driven in nature and require dynamic execution time. Xtreme behavioral processors enable the following for acceleration and emulation: · Runtime triggering and monitoring · Automatic and efficient memory mapping (for most types of memory, including complex memory such as CAMS) · Large arithmetic operations used in datapath-intensive designs · Behavioral assertion processor technology without gate-count explosion · Event-driven processing that can sequence operations requiring a dynamic number of steps HW/SW CO-VERIFICATION The combination of an Incisive Xtreme accelerator/emulator with software models of ARM® processors and a co-verification model of an ARM CPU (with the Xtreme series) provides the most advanced debugging solution for ARM designs and the necessary functionality at each stage of the verification lifecycle. The Xtreme series provides a comprehensive, leading-edge methodology for ARM SoC verification using a unified toolset for HW/SW engineers to verify and debug designs containing ARM microprocessors. In one package, the Xtreme series provides mixed-HDL logic simulation, simulation acceleration, in-circuit emulation (ICE), HW/SW co-verification using either software models of the ARM CPU or hardware models of the ARM CPU using ICE, and AMBA® bus testbench development. COMPLETE HISTORY WITHOUT RE-SIMULATION The Xtreme value-change-dump (VCD) on-demand feature gives you access to all node history values from any point in simulation, without re-simulating from time zero. Waveforms can be generated in either IEEE-standard VCD, fast signal database (FSDB), or SimVision (SST2) format. IN-CIRCUIT EMULATION WITH XTREME III SYSTEM Xtreme III System and Xtreme Server can connect directly to a target system and are controlled through a Solaris or Linux workstation for compactness and high-speed communication. The ability to emulate physical hardware with software models simultaneously while also using a software simulation environment for debugging provides the most flexible and accessible system integration solution available. ADVANCED BEHAVIORAL EMULATION AND PROCEDURAL CALLBACKS To address performance bottlenecks as well as overall simulation speed, Cadence has developed several innovative technologies in the Xtreme series of accelerators/ emulators. These include an event-based system control, the capability of direct testbench procedural calls from hardware, and behavioral processor technology in hardware. Leveraging this unique hardware architecture, designers or application engineers can map behavioral Verilog constructs or testbench code by hand into equivalent synthesizable RTL code, thus obtaining improved acceleration speed. COMPREHENSIVE SET OF APPLICATION-SPECIFIC SOLUTIONS Cadence offers a comprehensive set of application-specific solutions to allow rapid adoption of emulation technology. [. . . ] The synthesizable RTL part of the transactor is moved into the hardware engine. The C/C++/SystemC code running on the workstation is interfaced to the accelerator through the SCE-MI­based interface. This can deliver higher performance than an HDL-based testbench. CADENCE SERVICES AND SUPPORT · Customer-focused solutions that increase ROI, reduce risk, and achieve your design goals faster ­ Collaborative approach and design infrastructure -- virtual teaming ­ Proven methodology and flow tuned to your design environment ­ Design and EDA implementation expertise · Product and flow training to fit your needs and preferred learning style ­ More than 80 instructor-led courses ­ certified instructors, real-world experience ­ More than 25 Internet Learning * Please check with Cadence Support for the most up-to-date information on SVA. INCISIVE VERIFICATION IP FOR TRANSACTION-BASED ACCELERATION Incisive Verification IP (VIP) for transactionbased acceleration (TBA) allows you to run an Incisive simulator either in standalone simulation mode or in TBA mode with total congruency of results. [. . . ]