User manual CADENCE DESIGN SYSTEMS INCISIVE VERIFICATION KIT DATASHEET

[. . . ] INCISIVE VERIFICATION KIT ENABLING METRIC-DRIVEN VERIFICATION DATASHEET VERIFICATION CHALLENGES Functional verification challenges have never been so great. With ASICs now in the multi-million gate range, verification engineers need to generate and manage thousands of tests, deal with frequent changes to the specification and project plan, and coordinate multiple teams/ sites. [. . . ] The kit is based on a real design and verification flow that you can use to improve your skills, leverage "best practices" examples, or use as a comprehensive "how to" reference. Cadence Help/Kit GUI Interface Workshops and Hands-On Labs Verification Environment/VIP Reference Design IP Level SoC Level Figure 1: Incisive Verification Kit INCISIVE VERIFICATION KIT The kit offers a comprehensive verification solution tailored to engineers developing IP blocks to complete SoCs. The environment contains verification methodologies and flows, a realistically challenging reference design, and an advanced metric-driven verification methodology. It also integrates many components from the Cadence portfolio of reusable verification IP (sold separately). The kit can be leveraged to develop your own environment, or can be a learning tool with its interactive design/verification navigator and integrated Cadence "CDNS Help" system. KIT BENEFITS · Acceleratesandeasesadoptionofnew verification technologies and methodologies · Increasespredictabilitybyautomating the verification management and analysis process · Improvesverificationproductivityby demonstrating how to maximize verification throughput (optimal coverage per cycle) · Reducesriskandensuresquality through realistic golden verification examples · Testbenchanddesignsbasedonstandard OVM languages: e, SystemVerilog, SystemC®, as well as Verilog® and VHDL · Showshow-toandbestpracticeswith easy-to-follow hands-on labs productivity of their verification process and, ultimately, the quality of their design. The Incisive Verification Kit demonstrates the methodologies and capabilities in the form of workshops, hands-on labs, and tutorial documentation, with the ability to automatically invoke the needed Incisive tool or VIP. The kit addresses the verification of both hardware and device software KIT COMPOSITION AND INTEGRATION The Incisive Verification Kit demonstrates multiple verification flows on an OpenCores RISC processor design. The platform consists of both Cadence and third-party IP integrated using AMBA® APB, AHB, AXI, and multi-layer AHB bus fabrics. The kit contains documented best practices and "golden" executable verification plans. There are two levels of the kit, both of which are supplied with Incisive Enterprise Simulator: the IP-level kit for IP creators and the SoC-level kit for SoC creators. Both the IP and SoC kits use Cadence Verification IP or Universal Verification Components (UVCs). [. . . ] It showcases the next methodology beyond coveragedriven verification, which is metricdriven verification, enabling users to significantly improve the predictability and OVM Simulation Verification IP Planning/Management Formal Verification Emulation/Acceleration Figure 2: Components of Metric-Driven Verification Low-Power Verification Mixed-Signal Verification Metric-Driven Verification Constrained-Random Verification Assertion-Based Verification HW/SW Co-Verification www. cadence. com INCISIVE VERIFICATION KIT 2 REFERENCE DESIGN HIGHLIGHTS · AMBA-basedSoCdesign · IntegralCadenceandthird-party design IP · Devicedriversforallmajorcomponents · Low-powerdomains · UARTdesignandsubsystemfor IP-level kit · MIPIandUSB3. 0designIPprovidedby Arasan Chip Systems, Inc. AHB-APB Bridge AHB Matrix OpenCores RISC Boot ROM On-Chip SRAM ODMA Controller ARASAN MIPI CSI ARASAN MIPI DSI ARASAN USB 3. 0 SMC ENET AXI2A HB W2AHB AHB-APB Bridge APB Bus #2 VERIFICATION ENVIRONMENT HIGHLIGHTS · IntegratedCDNSHelpenvironment · Kitisupdatedwitheachmajorrelease of the Incisive platform · KitlicenseisincludedwithIncisive Enterprise Simulator, Incisive Formal Verifier, and Incisive Enterprise Verifier · Integratedmetric-drivenverification techniques utilizing Incisive Enterprise Manager and Cadence VIP portfolio · Sourceformatformanydesignand verification components · Low-powerandmixed-signalverification techniques demonstrated throughout the kit · Real-worlddesign/real-worldverification environment to maximize learning Figure 3: SoC-Level Block Diagram Interrupt Controller Triple Timer GPIO APB Bus #1 ALUT UART0 UART1 PCM Watchdog Timer Clock/ PLL Low-Power Domains INSTALLATION INFORMATION · Ethernet10/100designIPisencrypted demonstration block provided by Cadence, and separately licensed outside of kit usage · Embeddedsoftwareandhardware/software co-verification flows require GNU tools for the OpenCores processor · Thekitisdeliveredasatarballoperating within a Linux environment · IPKit­FocusedonUARTsubsystem · SoCKit­FocusedoncompleteSoC · Thekitdocumentationsystem(CDNS Help) can be extracted from the Linux installation and installed on Windows · IncisiveVerificationKit­IPLevel is licensed with Incisive Enterprise Simulator XL, Incisive Formal Verifier, Incisive Enterprise Verifier, and Specman · IncisiveVerificationKit­SoCLevel is licensed with Incisive Enterprise Simulator XL and Incisive Enterprise Verifier For more information contact Cadence sales at: +1. 408. 943. 1234 or log on to: www. cadence. com/ contact_us © 2009 Cadence Design Systems, Inc. Cadence, the Cadence logo, Encounter, First Encounter, Specman, and Verilog are registered trademarks of Cadence Design Systems, Inc. [. . . ]