User manual CADENCE DESIGN SYSTEMS INCISIVE ENTERPRISE SPECMAN PRODUCTS DATASHEET

[. . . ] C, C++, SystemC Embedded Software Incisive Acceleration and Emulation Figure 1: Incisive Enterprise Specman Elite Testbench helps drive the entire process of verification at block, chip, system, and project levels. The Verification Builder, Scenario Builder, and eAnalzyer components automate the creation and configuration of reusable, scalable, eRM-compliant environments and stimuli. The Specman ESL option offers a high-throughput channel between the testbench and the DUT, and enables access to embedded software as if it were another part of the DUT. INCISIVE ENTERPRISE SPECMAN ELITE TESTBENCH Successful verification of today's multimilliongate designs requires optimal speed and efficiency. [. . . ] They can even generate tests on-the-fly based on the current design state, making it possible to detect hard-to-reach corner cases. DATA AND ASSERTION CHECKING Powerful temporal constructs allow verification specialists and designers to capture complex protocols for assertion checking. On-the-fly data checking and generation provides context-specific expected values. With Specman products, verification engineers can use any combination of gray-, black-, or white-box checking to speed debugging. www. cadence. com INCISIVE ENTERPRISE SPECMAN PRODUCTS FUNCTIONAL COVERAGE ANALYSIS An executable functional test plan measures the progress of verification, and functional analysis automatically identifies holes in the test coverage. Since functional coverage is a meaningful and direct measure of the completeness of verification, functional coverage analysis increases predictability in verification schedules. RAPID CREATION OF LIBRARIES OF REUSABLE TESTS Specman products fully support the testbench reuse component of the Plan-to-Closure Methodology, which describes how to create reusable verification components in any IEEE-standard language, and provides guidelines for setting up multi-language interfaces to existing IP for maximum operational flexibility. The process is based on the time-tested e Reuse Methodology (eRM) and System Verification Methodology (SVM). With the Specman Verification Builder component, users can quickly create and configure reusable verification components in eRM-compliant format. Verification Builder also supports plug-ins that help users automatically connect the DUT to the testbench. A similar plug-in for the Specman ESL option (see below) supports rapid binding of the testbench to the processor model(s). The Specman Scenario Builder component helps designers create test cases in a fraction of the time it would take to write them in a hardware verification language, eliminating the need to learn a verification language and object-oriented programming. Users simply drag-and-drop randomized verification elements and adjust their constraints to build a scenario. Scenario Builder makes it just as easy to build complex system-level test cases: users define stimuli for each interface that can be synchronized on existing or user-defined events. When combined with the "sequence" feature of the Plan-to-Closure Methodology, stimuli that exercise corner-case scenarios at the block level can be reused at the system level to verify how the entire chip behaves in that corner case. Furthermore, users can graphically create these sequences as easily as test cases, which they can use in other tests hierarchically or in other sequences by dragging and dropping in a new scenario. All scenarios are written out into a reusable format, supporting the creation of portable libraries of protocol checkers and other structured behaviors for reuse on future projects, or system-level verification of the same project. models including mixed SystemC/RTL environments, and co-verify SystemC models used for software development. In addition to supporting Incisive simulators, Specman products provide interface adaptors for SystemC simulators including OSCI® and CoWare ConvergenSC. With Specman technology, engineers can create a single verification environment to verify their SystemC model and then reuse it throughout the entire downstream flow, from RTL simulation to acceleration and emulation. TESTBENCH STATIC ANALYSIS Static analysis catches testbench bugs and coding surprises early in the verification cycle. It performs more than 200 checks to flag syntactic, semantic, and functional errors. A flow that includes testbench analysis before simulation will check the code for reusability per eRM-compliance rules, testbench performance issues, race conditions, pre-defined coding style rules, generation constraints, and semantic ambiguities. [. . . ] The result: rapid discovery of deeply buried, cross-domain bugs that are impossible to find otherwise. TRANSACTION-BASED ACCELERATED (TBA) Transaction-based acceleration (TBA) technology utilizes message-level communication between the Specman testbench and the acceleration/emulation hardware. By communicating at the message level instead of the signal level, "TBA Specman" significantly reduces the amount of testbench-DUT communication, greatly increasing overall throughput over simulation alone (up to 100x when used in combination with the Incisive Palladium® or Xtreme® series of hardware accelerators and emulators). This level of performance enables full system-level validation that includes embedded and application layer software. [. . . ]