User manual CADENCE DESIGN SYSTEMS INCISIVE ENTERPRISE PALLADIUM SERIES WITH INCISIVE XE SOFTWARE DATASHEET

[. . . ] With Palladium technology, regression runs are compressed from months to hours; overnight tests will complete during a coffee break. IN-CIRCUIT EMULATION For final system verification, in-circuit emulation mode runs up to or more than 1, 000, 000x faster than simulation on large designs, and it incorporates peripherals, embedded processors, multiple ASICs, and embedded software into a single environment. This level of performance enables the ultimate goal of SoC verification--comprehensive application-level system and software testing. Palladium III vs. Palladium II 1. 7x 2x 3x 10x+ 7x 2x Same Same Up to 3x Same Same FIRST SILICON, FIRST SOFTWARE Palladium systems address demanding time-to-market requirements by enabling concurrent, automated, and managed verification of hardware and embedded software. As more and more electronic products have extensive software content, designers face serious project delays if they wait until silicon is available to begin debugging. [. . . ] You can migrate from system-level modeling to RTL verification and reuse your testbench to verify the accelerated design. · Assertion-based acceleration Assertion-based acceleration provides full interoperability by accelerating the assertions through the use of Palladium assertions. · Verification IP for in-circuit emulation SpeedBridge® rate adapters provide an interface to testers and real-world systems. SpeedBridge adapters connect emulated designs to environments running at 10s of MHz. The following SpeedBridge adapters are available today: ­ ­ ­ ­ ­ ­ PCI/PCIX SpeedBridge PCI Express SpeedBridge Audio/Video SpeedBridge Multi-Ethernet SpeedBridge SAS/SATA SpeedBridge USB SpeedBridge ­ Xilinx Virtex-II FPGA for prototyping discrete logic outside the emulator ­ Generic pin-grid array for usermounting of any discrete components · Transaction-based acceleration Transaction-based acceleration (TBA) is an acceleration mode that supports a transaction-oriented testbench modeling style. TBA uses message-level communication between the SystemC testbench components running on the workstation and the rest of the environment running on the Palladium system. By using message-level communication rather than signal-level communication, TBA reduces the amount of communication and thereby increases overall acceleration performance. Unique productivity features, including support for variable length messages, faster streaming mode, and transaction recording, are available with Palladium TBA. Incisive XE software supports a timed modeling style of testbench components in addition to an untimed modeling style. The Incisive Enterprise Simulator has also been optimized to provide high-speed, low-latency communication with the Palladium system, further increasing performance. ­ Congruent TBA: allows users to create a transaction-based environment without using the hardware. Using only the Incisive Enterprise Simulator, engineers can fully develop their models, optimizing environment bringup time. Once the models are fully functional, engineers then migrate painlessly to hardware, where these same models will run unchanged at up to 100x faster than standard simulation. With congruent TBA, results are guaranteed to be the same, regardless of which engine (Incisive or Palladium) is used for execution ­ Concurrent TBA: allows users to achieve near-emulation performance with designs being driven from a testbench. With this mode, the design runs continuously (free running) at full emulation speed, while the testbench is running on the workstation. This exclusive feature is ideal for running large regression suites, where maximum performance is essential Figure 5: Palladium series IP chassis · TBA VIP The Palladium series supports a suite of industry-standard transactors such as PCI Express, Ethernet, AMBATM AHB, and AXI. · ABA VIP The Palladium series supports a suite of industry-standard protocol monitors built from assertions including USB, Ethernet, AMBA AHB, and AXI. MULTIPLE USE MODELS FOR MAXIMUM VALUE · Signal-based acceleration Signal-based acceleration with Palladium systems delivers up to 1, 000x performance over simulation and is a natural first step when the need for verification performance increases. The synthesizable RTL and memory models are moved into the accelerator where they run several orders of magnitude faster than on the workstation. Because performance can be limited by the behavioral code running on the workstation, the Palladium system utilizes a unique signal-guided synchronization algorithm that reduces the communication between the workstation and the accelerator. The Palladium system's Incisive XE compiler also synthesizes many behavioral statements, which further improves performance. These technologies greatly increase performance compared with earlier acceleration technologies. Figure 4: Universal SpeedBridge chassis · IP blocks Palladium systems support hard IP with standard IP blocks through the Palladium IP chassis. Each standard IP block is 100x175mm in size and can have up to 1, 248 bi-directional signal pins. [. . . ] For designs less than 20M gates, workstations require 200MB RAM for each million gates of design size with a minimum of 2GB. Palladium Simulation acceleration communication channel Palladium to host workstation 3. 3V PCI slot Palladium II/III 61, 440 192 192 1/3X CMOS3. 3V, 2. 5V, 1. 8V, 1. 5V, LVDS, HSTL, SSTL 5. 3ns FLEXIBLE ALLOCATION OF CAPACITY Palladium systems allow the total capacity to be dynamically allocated among users in "domains. " For example, if nine domains are available in a system, user A can use two domains for simulation acceleration while user B runs in-circuit emulation of a larger design with the other seven domains. When both are finished, user C might use all nine domains for an even larger design. Palladium Maximum capacity Domain capacity Domains per board Gates per board Memory per board Maximum speed Palladium II Palladium III 7. 5ns Palladium II/III 3. 3V PCI slot FLEXIBLE CLOCKING Palladium systems support both internally generated and externally supplied clocks. Palladium systems utilize unique algorithms that enable them to handle any number of synchronous, asynchronous, and gated clocks, either internal or external, while maintaining high levels of performance. When used for simulation acceleration, a variety of simulator synchronization techniques are available to maximize performance over conventional lockstep synchronization. FibreChannel one 3. 3 or 5V PCI slot FibreChannel and gigabit Ethernet: two 3. 3 or 5V PCI/PCI Express slots Up to 128M Up to 256M Up to 256M gates gates gates 1M gates 8 8M 4GB 750KHz 1. 8M gates 9 16M 4. 6GB 1. 5MHz 1. 8M 9 16M 4. 6GB 2MHz OPERATING SYSTEM SUPPORT · Sun Solaris (32-bit, 64-bit) · Linux PC (32-bit, 64-bit) · HP-UX (32-bit) SIMULATION ACCELERATION KITS Simulation acceleration kits provide a high-bandwidth, low-latency connection between Palladium hardware and a PCIor PCI Express-compatible workstation. [. . . ]