User manual CADENCE DESIGN SYSTEMS ENCOUNTER CONFORMAL CONSTRAINT DESIGNER DATASHEET

[. . . ] ENCOUNTER CONFORMAL CONSTRAINT DESIGNER DATASHEET ENCOUNTER CONFORMAL CONSTRAINT DESIGNER Validating, modifying, and creating the SDC timing constraints required for design implementation and static timing analysis (STA) signoff have conventionally involved manual and inefficient processes. Encounter Conformal Constraint Designer enables efficient development and management of constraints, ensuring they are functionally correct--from RTL to layout. By delivering higher quality timing constraints early and throughout the flow, it helps designers reduce overall design cycle times and enhances quality of silicon for even the most challenging SoC designs. [. . . ] Implementation and STA tools may have inconsistent precedence rules or select pessimistic constraints, which result in poor quality of silicon. Designers must have an opportunity to review the conflicts and decide on the proper course of action. Conformal Constraint Designer reports duplicated or overwritten constraints and overlapping exceptions, so designers can accomplish this task efficiently and formally. HIERARCHICAL CONSTRAINT CHECKS Block designers typically write SDC independently from top-level constraints. When chip integrators or physical designers assemble the chip, they may find that the constraints have conflicts in terms of clock definition, set I/O delay settings, and exceptions. Conformal Constraint Designer can quickly and easily detect these errors early in the design cycle with hierarchical constraint checks. It checks the SDC of the design at different hierarchical levels--chip-level SDC vs. block-level SDC--and pinpoints conflicts, overlap, or other issues related to clocks, SDC COMPARE Duringthedesignprocess, optimization tools may transform reference objects in the design. The impact of adding or deleting timing constraintscanbeobserved;forexample, the impact of adding a timing exception upon the rest of the design. It can check before-and-after, or can be used Figure 2: For an invalid false path exception, Encounter Conformal Constraint Designer can show the path of concern and a waveform that triggers it www. cadence. com ENCOUNTER CONFORMAL CONSTRAINT DESIGNER 2 SDC INTEGRATION Given a set of block-level constraints, Conformal Constraint Designer can generate the top-level constraints through the use of default or user-defined precedence rules, easing the process of assembling the design for placeand-route. FALSE-PATH GENERATION FROM RTL Conformal Constraint Designer can generate meaningful false-path statements directly from the RTL, which accelerates timing closure. As with timing report validation, these new exceptions are the product of formal validation. Figure 3: Clock Domain Crossing checks as viewed in helix extensible platform CLOCK DOMAIN CROSSINGS Clocks are defined within SDC constraint files. Checking for structural issues with clock domain crossings (CDC) is a perfect task for Conformal Constraint Designer while the quality and consistency of timing constraints is checked. The false paths can also be found in asynchronous behavior of designs, and analysis and validation of these paths are performed accordingly. A counter-example is generated when validation fails, quickly pinpointing the active path and the waveform that enables it. TIMING REPORT VALIDATION Designers can spend enormous amounts of time debugging timing reports to separate functional false paths from true ones. Conformal Constraint Designer automates and accelerates this validation process by identifying false paths from critical timing reports and generating new SDC exceptions. These results can be used to improve synthesis, place-and-route, or STA results. By focusing only on paths that violate timing, the generation is quick, relevant, and accurate (as it is done through formal validation). For example, it reveals the structures of any undefined clocks, allowing the user to constrain them quickly and completely. All that is needed is to fill in the blanks, such as clock frequencies. [. . . ] SDC quality and hierarchical checks can be invoked from the synthesis (quality only), place-and-route, and STA environments, displaying any constraint conflicts or inconsistencies. These issues are often revealed only during integration of the different blocks. Furthermore, timing report validation (TRV) can be run by Conformal Constraint Designer from within all three Encounter implementation technologies. [. . . ]