User manual CADENCE DESIGN SYSTEMS CADENCE PALLADIUM XP TECH BRIEF

[. . . ] Palladium XP removes the barrier to entry in acceleration and emulation by offering a unified environment that leverages the native simulation environment and allows a Cadence Incisive simulator user to hot-swap among simulation, simulation acceleration, and emulation environments at runtime without re-compilation. Palladium XP can be used at various design and verification phases, from early architectural analysis and block-, chip-, and system-level integration to software development and system verification. Architecture Exploration Algorithmic Verification Block/IP Verification Chip-Level Verification Firmware Verification Software Verification Field Prototype Simulation Simulation Acceleration Emulation Figure 4: Palladium XP removes barriers to scalable performance with a unified flow and allows users to easily transition among simulation, simulation acceleration, and emulation Furthermore, Palladium XP improves verification productivity by offering the fastest bring-up time, an easy-to-use flow, flexible simulation-like use models, scalable performance, and fast and predictable compile for the best turnaround time. It is designed to interface with real-world stimulus and enables hot-swap into the simulation environment while providing early access to HW/SW co-verification and advanced debug. www. cadence. com PALLADIUM XP VERIFICATION COMPUTING P L AT F O R M 2 Palladium XP offers enhancements above and beyond what traditional acceleration and emulation use models offer. Palladium XP introduces new use models to improve verification productivity through metric-driven verification acceleration, hardware verification language-based testbench acceleration, Open Verification Methodology (OVM) acceleration, and system-level power verification. Open Verification Methodology for Acceleration Synthesizable Testbench Metric-Driven Verification for Acceleration In-Circuit Emulation OVM MDV STB UXE Unified Xccelerator Emulator Software ICE Vector-Based Acceleration VBA Debug Advanced Debug TransactionBased Acceleration TBA VIP Verification Intellectual Property Assertion-Based Acceleration ABA Signal-Based Acceleration Palladium XP Hardware XL, GXL DPA Dynamic Power Analysis SBA PSO Power Shutoff Verification Figure 5: Palladium XP offers comprehensive use models for HW/SW co-verification and system realization PALLADIUM XP BENEFITS · Highest scalability and flexibility ­ Enables centralized or locally distributed verification computing with scalable resources to serve a single user or as many as 512 simultaneous users for up to 2 billion gates capacity ­ Supports flexible executable functional models at various abstraction levels (C/C++, SystemC®, instruction set or cycle accurate, silicon, RTL, gates) ­ Offers flexible use models and flexible resource allocation · Unparalleled verification computing productivity ­ Integrates seamlessly with the simulation environment for multi-user productivity ­ Facilitates best turnaround time with efficient compile, runtime performance of up to 4MHz, and simplified but superior at-speed and offline debug capabilities ­ Reduces the learning curve with an easy-to-use flow, from simulation to acceleration to emulation, by leveraging the existing simulation environment www. cadence. com PALLADIUM XP VERIFICATION COMPUTING P L AT F O R M 3 · Better design bring-up predictability ­ Enables quick bring-up with its fast, automated, intelligent compiler that includes a rich set of behavior construct support and congruent (match) behavior between simulation and hardware ­ Boosts runtime predictability with "hot-swap" to acceleration or emulation and the most flexible use models ­ Enables quick system-level bring-up with comprehensive and proven Cadence SpeedBridge® portfolio (comprising hardware rate adapters for external targets) · Platform extension ­ Supports metric-driven verification for acceleration with coverage and advancements in hardware verification/hardware design languages ­ Supports the most comprehensive hard or soft verification IP for standard protocols ­ Enhances system-level low-power analysis with Dynamic Power Analysis option and power verification techniques such as power shutoff PALLADIUM XP FEATURES COMPREHENSIVE VERIFICATION COMPUTING PLATFORM The Palladium XP verification computing platform is state-of-the art for its advancements in hardware, software (compilation, debug, runtime, flexibility), and use models. [. . . ] Unlike other systems, Palladium XP supports both static and dynamic targets, so it interfaces easily with virtually any target environment. When interfacing with a real-world environment, it is sometimes necessary to control the relative timing of individual output signals from the emulator. Palladium XP provides direct support for all popular signal interfaces and has a vast number of I/O pins to support even the largest multi-user environments. Its UXE software can support HDL files encrypted by IP providers for protection, giving access only to the signals and registers permitted by that IP provider. Bonded-out microprocessor cores, silicon cores, or FPGA logic can be installed into the Palladium IP chassis using standard Cadence IP blocks, making it easy to utilize hard IP during verification. Palladium XP is fully compatible with the complete family of Cadence SpeedBridge Adapters, providing simple and direct integration with full-speed in-circuit verification environments. Each SpeedBridge product is a transparent speed/rate adapter that connects real-world systems with the design being emulated. Palladium XP can also take advantage of recent software enhancements for controlling various functions through the GUI, such as soft reset of the board and remote configuration. SpeedBridge Adapters are an option to Palladium XP. www. cadence. com PALLADIUM XP VERIFICATION COMPUTING P L AT F O R M 7 USB Device PCI Express USB Host PCI/PCI-X SAS Interface to ThirdParty IP and Testers Palladium XP Verification Computing Platform SATA Wireless Video/ Audio MultiEthernet Multi-I/O Fibre Channel Figure 8: For most industry-standard protocols, off-the-shelf VIP such as SpeedBridge Adapters are available, enabling SoC designs running on Palladium XP to interface with real-world devices/targets/testers for system-level verification TRANSACTION-BASED ACCELERATION Transaction-based acceleration (TBA) is an optimized simulation acceleration mode that supports a transaction-oriented testbench modeling style. TBA uses message-level communication between the testbench components running on a workstation and the rest of the environment running on the Palladium XP platform. By using message-level communication rather than signal-level communication, TBA reduces the amount of communication overhead between the workstation and the emulator, thereby increasing overall acceleration performance. · Congruent TBA allows users to create a transaction-based environment without using the hardware. Using only a simulator, such as Incisive Enterprise Simulator, engineers can fully develop their models and optimize environment bring-up time. Once the models are fully functional, engineers can then migrate painlessly to hardware, where these same models will run unchanged yet faster than with standard simulation. With congruent TBA, results are guaranteed to be the same, regardless of which engine (Incisive or Palladium XP) is employed. · Concurrent TBA allows users to achieve near-emulation performance with designs being driven from a testbench. In this mode, the design runs continuously (free running) at full emulation speed while the testbench is running on the workstation. This unique feature is ideal for running large regression suites, where maximum performance is essential. Palladium XP employs an Accellera standardized interface--SCE-MI--and SystemVerilog DPI to simulators with support for standard and advanced testbench languages, including SystemVerilog, SystemC, and C/C++. www. cadence. com PALLADIUM XP VERIFICATION COMPUTING P L AT F O R M 8 HYBRID ENVIRONMENT A hybrid of hardware and software verification IP (VIP) models can be used for increased predictability and productivity earlier in the design cycle. To complement TBA mode and further reduce design schedules, Cadence offers off-the-shelf VIP optimized for acceleration for various industry-standard protocols, as well as SpeedBridge Adapters optimized for emulation interfaces to various processor models, debuggers, and testers. Users can connect their VIP using a transaction-level modeling (TLM) interface and combine virtual prototyping with acceleration and emulation in a hybrid environment. The benefit of a hybrid environment is that users can achieve the best performance by leveraging available IP in the most flexible way. [. . . ] This helps verify protocol layers (full stack) while running software applications and debug issues. SPECIFICATIONS Palladium XP is available in two main configurations: XL and GXL. They share a common architecture (MCM, memory cards, cables, software), providing the same functionality; however, they differ in physical characteristics and scalability requirements. Palladium XP (XL) Scalable capacity and I/O · I/O: Up to 3, 072 · CMOS3. 3V, 2. 5V, 1. 8V, 1. 5V, LVDS, HSTL, SSTL Default dedicated user memory Simultaneous users Architecture Design format and language support Up to 16 gigabytes From 1 to 8 users Palladium XP (GXL) · I/O: Up to 147, 456 · CMOS3. 3V, 2. 5V, 1. 8V, 1. 5V, LVDS, HSTL, SSTL Up to 1 terabyte From 1 to 512 users · Capacity: Up to 32 million gates · Capacity: Up to 2 billion gates Custom advanced processors (MCMs) · HDL: RTL (VHDL, Verilog, SystemVerilog) and gate-level netlist · HVL: C++, SystemC, Specman `e', SystemVerilog, and Open Verification Methodology (OVM) acceleration · Assertions: System Verilog Assertions (SVA), Property Specification Language (PSL), Incisive Assertion Library, and Open Verilog Library (OVL) Memory transformation Options for memory placement, compaction, squeezing, read port splitting, and merging www. cadence. com PALLADIUM XP VERIFICATION COMPUTING P L AT F O R M 12 Palladium XP (XL) HW/SW interfaces, connecting to third-party tools/IP/environment Palladium XP (GXL) · Various standards: SCE-MI 1. 1/2. 0 and TLM support · Most comprehensive SpeedBridge portfolio for standard protocols supporting most market segments · Application-specific interfaces: C/C++, PLI, VPI, SystemVerilog DPI, DPI-SystemC, VHPI, etc. and support for third-party interfaces to the standalone UXE model Fast compile Performance Advanced debug Up to 35 million gates per hour with a single workstation for RTL Up to 4MHz, with built-in profiler that tunes performance for acceleration · FullVision: see any signals with longer trace depth, unified database, tight integration with Incisive Enterprise Simulator and SimVision (up to 2 million samples) · Enables assertions and transaction viewing · InfiniTrace, hot-swap, triggers on simple to complex events, support for subset of system tasks · Dynamic probes and virtual probes with fast upload time (up to 20 million cycles) ­ superfast incremental upload, State Description Language (SDL) for hardware designers, integrated debug environment, and third-party SW debuggers and various hard/soft IP supporting HW/SW co-debug and co-verification · Power profile along with design signals in SimVision GUI Flexible clocking Supports a very large number of synchronous, asynchronous, and gated clocks WORKSTATION REQUIREMENTS In addition to simulation acceleration connections to individual workstations, each Palladium XP system uses a host workstation. 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