User manual CADENCE DESIGN SYSTEMS CADENCE LITHO PHYSICAL ANALYZER DATASHEET

[. . . ] CADEnCE LiTHO PHySiCAL AnALyzER DATASHEET CadenCe Litho PhysiCaL anaLyzer At 65 nanometers and below, lithography, etch, and mask systematic manufacturing variations surpass random variations as the prime limiters to catastrophic and parametric yield loss. The interaction of manufacturing shapes within the optical proximity halo and the spatially partially-coherent lithography projection systems creates highly non-linear systematic variations at different process conditions that cannot be captured by rules or pattern matching. [. . . ] Running post-GDSii OPC tools during layout is not feasible, because it takes days for every layer to run a typical design through OPC. Designers can restrict their design style in an attempt to improve yield, but this method limits the use of leadingedge processes that optimize area and performance. Only model-based predictive approaches (that are not based on moving post-GDSii OPC tools to the designer's desk) are fast enough to let designers uncover hotspots during design implementation and make real-time design adjustments to eliminate them. Cadence Litho Physical Analyzer is a full-chip, model-based design manufacturability checker--silicon-proven and endorsed by all major foundry platforms-- that designers can use to find and fix hotspots and predict contours across process conditions. it uses a patentpending, model-based, non-linear optical transformation algorithm that allows designers to quickly and accurately detect potential manufacturing failures during physical design that would otherwise be found after tapeout in mask or silicon. The compact models encapsulate all necessary RET, OPC, mask, etch, and lithography effects on both device and interconnect, and predict accurate contours for the entire chip from drawn layout in a matter of hours. Cadence Litho Physical Analyzer is typically an order of magnitude faster than other model-based tools. features ModeL-Based ManufaCturing shaPe PrediCtion Traditional approaches to deal with manufacturing variations are no longer adequate. Design rule checking (DRC) alone does not prevent catastrophic yield loss due to systematic shape variations; additionally, DRC rules to address growing DFM issues become prohibitive in number and complexity. Post-GDSii OPC uncovers printability problems that frequently soPhistiCated hotsPot deteCtion and CorreCtion guideLines Litho Physical Analyzer identifies hotspots based on fab-designated criteria or litho yield sensitivity (LyS) metrics. it sorts hotpots by type and criticality, and prechecked blocks can be excluded by name, area, or marker layer. The non-linear optical transformation algorithm also allows generation of automatic fixing guidelines that are input into the user's choice of physical design tools, such as Cadence Virtuoso® Layout Suite and www. cadence. com C ADE nCE Li THO PHy SiCAL AnALyzER Cadence Chip Optimizer. Litho Physical Analyzer integrates with current library, iP, custom analog, and cell-based digital physical design flows. designer friendLy With a usage model similar to DRC, Litho Physical Analyzer works from layout and fab technology file input to produce a fullchip report that flags DFM hotspots such as opens and shorts, contact coverage, gate variability, and line-end pullback in the original layout. [. . . ] Litho Physical Analyzer is used by major foundries and their customers to systematically detect hotspots on designs prior to manufacturing. forMat suPPort · Design input: GDSii, LEF/DEF · Design output: GDS, HiF, DLD (contour database for Cadence Litho Electrical Analyzer) PLatforMs · Linux (32-bit, 64-bit) www. cadence. com C ADE nCE Li THO PHy SiCAL AnALyzER for more information, email us at info@cadence. com or visit www. cadence. com © 2008 Cadence design systems, inc. Cadence and virtuoso are registered trademarks and the Cadence logo is a trademark of Cadence design systems, inc. [. . . ]