User manual CADENCE DESIGN SYSTEMS CADENCE INCYTE CHIP ESTIMATOR DATASHEET

[. . . ] CAD E N C E I N C Y T E C H I P EST I M AT O R DATASHEET With the escalating costs of chip design, it is imperative that projects begin with careful planning to ensure that goals can be met and monitored for progress. [. . . ] This is useful for fabless semiconductor companies, integrated device manufacturers, ASIC vendors and customers, design services providers, and IP providers. Design Specification · Blocks, Gate Counts · Clocks, Constraints · Memory, IP, I/Os Estimation Results · Die Area · Power · Performance · Early Floorplan · Packaged Chip Cost · Customizable Reports · EDA Tool Input Data IP Catalog Data User-Defined IP Technology Models Figure 1: Size, performance, and power estimation algorithms combined with an extensive IP catalog enable early and accurate what-if analysis BENEFITS · Improvespredictabilityofsuccess - Closes early on a specification that best balances size, power, and costs - Uses real IP, process, and architecture data to determine specifications · Addressestheimpactofpowercomprehensively - Estimates power at the architectural level - Plansblock-levelandchip-levelpower strategies - Models different power modes - Generates a Common Power Format (CPF)filetodrivedownstreamimplementation · ProvidesaccesstoChipEstimate. com, the foremost IP ecosystem - 7, 000+ IP components from 200+ IP suppliers and foundries - Compares digital, analog, and mixed-signal IP in the context of your design, before contacting multiple IP providersdirectly - Providesawidesetofdesignoptions to explore · Quantifiesthecostimpactofchip architecture and implementation decisions - Draws on built-in economic and yield data · Reducesimplementationrisk - Enables early planning followed by a convergentflow - Passes architecture and library data forwardtodriveimplementation tools - Feeds back implemented block data to refine accuracy of the model and todrivein-projectdecisions · Ease-of-useenablescollaboration - Promotes communication among business and technical teams - Starts with early planning and continues throughout the course of the project · Editthefloorplanviewtoanalyze impactofmovementandrotationon size, power, performance, and cost · Exportthedesignintentdownstreamto synthesis, low-powerverification, and physical implementation: DEF, LEF, high-levelVerilog®, CPF, SDC, synthesis scripts, implementation scripts, and compiled memory scripts FEATURES Cadence InCyte Chip Estimator operates in a client-server model and has the libraries you need already built-in. The client is the InCyte Chip Estimator application on your Windows or Linux desktop. The server brings that same IP catalog and foundry libraries from ChipEstimate. com directly into the client application. InCyte Chip Estimator is available in several different configurations. INCYTE CHIP ESTIMATOR XL InCyteChipEstimatorXLaddsadvanced analysis capabilities, including economic analysis, power profile analysis, and power management, on top of the core chip planning features of the L edition. · Vieweconomiclifecycletablesand graphs that offer cost analysis of yieldaffected wafers, packaging, test and assembly, and non-recurring engineering (NRE) charges · GeneratecompleteICeconomic analysis reports and budgetary quotes · Createpowerprofileswithvarious modes, assignpercentactivetimefor modes · Easilyincludeadvancedpower management techniques (power shutoff, multi-supply/multi-voltage, clock gating) while measuring the size and power impact of these techniques · Automaticallytakesintoaccountthe costoverheadofadvancedlow-power techniques · Visualizetheimpactoftechniqueson dynamic power, leakage power, size, and performance · Interfacesbi-directionallywithCadence Encounter® RTL Compiler synthesis solution - Feeds forward SDC, module definitions, floorplanhints, andsynthesis scripts - Feeds back synthesized gate counts of random logic blocks and compares to earlier estimates INCYTE CHIP ESTIMATOR L For accurate technical estimation of design size and power, InCyte Chip Estimator L combines foundry-specific models with the ChipEstimate. com IP portal inside an easy-to-use estimation environment. · AccesstheChipEstimate. comIPcatalog (built into the software) · Selectfoundry-specificfoundation libraries of standard cells, I/Os, and memories. · Selectaspecificfoundrylibraryata specific process node · Filterthebuilt-inIPcatalogtoshowIP suitable for that node · DefinecustomIPmacros · Estimatedesignsize · Estimatedesignpower(dynamicand leakage) · Comparesize, power, andperformance ofmultipledesignsordesignvariations · Estimateperformanceachievabilityin specific manufacturing processes with specific IP components · Createandeditablockdiagramofthe design using drag-and-drop for blocks anddrawingtoolsforconnectivity www. cadence. com CADENCE INCYTE CHIP ESTIMATOR 2 · Interfacesbi-directionallywiththe Encounter Digital Implementation System - FeedsforwardSDC, floorplanhints, and implementation scripts - Feeds back implementation metrics to enable economic analysis and compares to earlier estimates · InterfaceswithSpiritIP-XACTfor import/export · Supportscontrolandextensibilityof chip planning with Python shell interpreter INCYTE ENTERPRISE EDITION For companies with large amounts of in-house IP to share across geographically diverse development centers, Cadence offers an enterprise solution in the form of the Cadence Chip Planning System. It includes an in-house corporate server along with the Chip Planning System client that has all the functionality of InCyte Chip Estimator XL. [. . . ] Cadence, the Cadence logo, Encounter, and Verilog are registered trademarks of Cadence Design Systems, Inc. [. . . ]