User manual BIOSTAR U8668-D

[. . . ] This equipment has been tested and found to c omply with the limits of a C lass B digital device, pursuant to Part 15 of the FCC Rules . t hese limits are designed to provide reasonable protection agains t harmful interference in a residential installation. This equipment generates , uses and can radiate radio frequency energy and, if not ins talled and used in accordance with the instructions, may c ause harmful interference to radio communications . There is no guarantee that interference will not occur in a partic ular installation. [. . . ] When enabled, the typematic rate and typematic delay can be configured. Sets the rate at which a keystroke is repeated when you hold the key down. Sets the delay time after the key is held down before it begins to repeat the keystroke. This option will enable only individuals with passwords to bring the system online and/or to use the CMOS Setup Utility. Select version supported by the operation system running on this computer. A choice other than Non-OS2 is only used for OS2 systems with memory exceeding 64MB. Determines whether video BIOS will be copied to RAM for faster execution. This submenu allows you to configure the specific features of the chipset installed on your system. This chipset manages bus speeds and access to system memory resources, such as DRAM and external cache. The default settings that came with your system have been optimized and therefore should not be changed unless you are suspicious that the settings have been changed incorrectly. If you highlight the literal "Press Enter" next to the "DRAM Clock" label and then press the enter key, it will take you a submenu with the following options: DRAM Clock This item determines DRAM clock following 100MHz, 133MHz or By SPD. SDRAM CAS Latency When DRAM is installed, the number of clock cycles of CAS latency depends on the DRAM timing. Precharge to Active (Trp) This items allows you to specify the delay from precharge command to activate command. Active to CMD (Trcd) Use this item to specify the delay from the activation of a bank to the time that a read or write command is accepted. DRAM Command Rate This item controls clock cycle that must occur between the last valid write operation and the next command. If you highlight the literal "Press Enter" next to the "AGP & P2P Bridge Control" label and then press the enter key, it will take you a submenu with the following options: AGP Aperture Size Select the size of the Accelerated Graphics Port (AGP) aperture. Host cycles that hit the aperture range are forwarded to the AGP without any translation. AGP Master 1 WS Write When Enabled, writes to the AGP (Accelerated Graphics Port) are executed with one wait states. AGP Master 1 WS Read When Enabled, read to the AGP (Accelerated Graphics Port) are executed with one wait states. If you highlight the literal "Press Enter" next to the "CPU & PCI Bus Control" label and then press the enter key, it will take you a submenu with the following options: CPU to PCI Write Buffer When enabled, up to four Dwords of data. When disabled, a write buffer is not used and the CPU read cycle will not be completed until the PCI bus signals that it is ready to receive the data. When Enabled, writes to the PCI bus are executed with zero-wait states. [. . . ] Press Enter to access another sub menu used to configure the different wake up events (i. PCI, or Personal Computer Interconnect, is a system which allows I/O devices to operate at speeds nearing the speed of the CPU itself uses when communicating with its own special components. This section covers some very technical items and it is strongly recommended that only experienced users should make any changes to the default settings. When set to YES, BIOS will only initialize the PnP cards used for the boot sequence (VGA, IDE, SCSI). [. . . ]