User manual AOPEN AP5TC

[. . . ] AP5TC User's Guide Printed in Taiwan PART NO. : 49. 87907. 001 DOC. : AP5TC-1-E9801A AP5TC Mainboard User's Guide Document Number Model and Revision Manual Version Release Date : AP5TC-1-E9801A : For AP5TC revision 1. xx : English, revision A : Jan 9, 1998 More help for latest information: Taiwan USA Europe http://www. aopen. com. tw http://www. aopen-usa. com http://www. aopenamerica. com http://www. aopen. nl Copyright Copyright © 1998 by this company. No part of this publication may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language or computer language, in any form or by any means, electronic, mechanical, magnetic, optical, manual or otherwise, without the prior written permission of this company. ii Disclaimer This company makes no representations or warranties, either expressed or implied, with respect to the contents hereof and specifically disclaims any warranties, merchantability or fitness for any particular purpose. Any software described in this manual is sold or licensed "as is". [. . . ] A prompt asking you to enter your password appears on the screen every time you boot the system. To disable the security option, select Password Setting from the main menu, don't type anything and just press <Enter>. BIOS Features à PCI/VGA Palette Snoop PCI/VGA Palette Snoop Enabled Disabled Enabling this item informs the PCI VGA card to keep silent (and to prevent conflict) when palette register is updated (i. e. , accepts data without responding any communication signals). This is useful only when two display cards use the same palette address and plugged in the PCI bus at the same time (such as MPEQ or Video capture). In such case, PCI VGA is silent while MPEQ/Video capture is set to function normally. BIOS Features à OS Select for DRAM > 64MB OS Select for DRAM > 64MB OS/2 Non-OS/2 Set to OS/2 if your system is utilizing an OS/2 operating system and has a memory size of more than 64 MB. BIOS Features à Video BIOS Shadow Video BIOS Shadow Enabled Disabled VGA BIOS Shadowing means to copy video display card BIOS into the DRAM area. This enhances system performance because DRAM access time is faster than ROM. 3-9 AWARD BIOS BIOS Features à BIOS Features à BIOS Features à BIOS Features à BIOS Features à BIOS Features à C8000-CBFFF Shadow Enabled Disabled C800-CBFF Shadow CC00-CFFF Shadow D000-D3FF Shadow D400-D7FF Shadow D800-DBFF Shadow DC00-DFFF Shadow These six items are for shadowing ROM code on other expansion cards. Before you set these parameters, you need to know the specific addresses of that ROM code. If you do not know this information, enable all the ROM shadow settings. Note: The F000 and E000 segments are always shadowed because BIOS code occupies these areas. 3-10 AWARD BIOS 3. 4 Chipset Features Setup The "Chipset Features Setup" includes settings for the chipset dependent features. These features are related to system performance. Caution: Make sure you fully understand the items contained in this menu before you try to change anything. However, it may cause system unstable if the setting are not correct for your system configuration. 3-11 AWARD BIOS Chipset Features à Auto Configuration Auto Configuration Enabled Disabled When Enabled, the DRAM and cache related timing are set to pre-defined value according to CPU type and clock. Select Disable if you want to specify your own DRAM timing. Chipset Features à DRAM Timing DRAM Timing 60 ns 70 ns There to sets of DRAM timing parameters can be automatically set by BIOS, 60ns and 70ns. Warning: The default memory timing setting is 60ns to get the optimal performance. Because the specification limitation of INTEL TX chipset , 70ns SIMM can only be used with CPU external clock 60MHz. To use 70ns SIMM with 66MHz CPU external clock may result in unstable system behavior. Chipset Features à DRAM Leadoff Timing DRAM Leadoff Timing 11/7/3/4 10/6/3/3 11/7/4/4 10/6/4/3 The Leadoff means the timing of first memory cycle in the burst read or write. Actually, this item controls only page miss read/write leadoff timing and the clocks of RAS precharge and RAS to CAS delay. The four digital represent Read Leadoff/ Write Leadoff/ RAS Precharge/ RAS to CAS delay. For example, default is 10/6/3/3, which means you have 10-x-x-x DRAM page miss read and 6-x-x-x DRAM write, with 3 clocks RAS precharge and 3 clocks RAS to CAS delay. 3-12 AWARD BIOS Chipset Features à DRAM Read Burst (EDO/FP) DRAM Read Burst (EDO/FP) x444/x444 x333/x444 x222/x333 Read Burst means to read four continuous memory cycles on four predefined addresses from the DRAM. The default value is x222/x333 for 60ns EDO or FPM (Fast Page Mode) DRAM. Which means the 2nd, 3rd and 4th memory cycles are 2 CPU clocks for EDO and 3 clocks for FPM. The value of x is the timing of first memory cycle and depends on the "DRAM Leadoff Timing" setting. Chipset Features à DRAM Write Burst Timing DRAM Write Burst Timing x444 x333 x222 Write Burst means to write four continuous memory cycles on four predefined addresses to the DRAM. This item sets the DRAM write timing of the 2nd, 3rd and 4th memory cycles. The value of x depends on the "DRAM Leadoff Timing" setting. Chipset Features à Fast EDO Lead Off Fast EDO Lead Off Enabled Disabled This item enables fast EDO read timing, results 1 clock pull-in for read leadoff latency of EDO read cycles. It must be Disabled, if any FPM DRAM is installed. Chipset Features à Refresh RAS# Assertion Refresh RAS# Assertion 5 Clks 4 Clks This item controls the number of clocks RAS is asserted for refresh cycle. 3-13 AWARD BIOS Chipset Features à DRAM Page Idle Timer DRAM Page Idle Timer 2 Clks 4 Clks 6 Clks 8 Clks This item determines the amount of time in CPU clocks that DRAM page will be close after CPU becomes idle. Chipset Features à DRAM Enhance Paging DRAM Enhance Paging Enabled Disabled When Enabled, TX chipset will keep DRAM page open as long as possible according to enhanced method. Chipset Features à SDRAM (CAS Lat/RAS-to-CAS) SDRAM(CAS Lat/RAS-to-CAS) 2/2 3/3 These are timing of SDRAM CAS Latency and RAS to CAS Delay, calculated by clocks. They are important parameters affects SDRAM performance, default is 2 clocks. [. . . ] Make sure that pin 1 of the cable is connected to pin1 of the connector. If possible, use another peripheral to double check if the mainboard or the cable is defective. 2. Locate the CMOS jumper and follow the procedures on how to clear the CMOS. Load the BIOS optimal settings (AMI) or load BIOS default settings (Award). [. . . ]