User manual AMD AMD64 ARCHITECTURE

[. . . ] AMD64 Technology AMD64 Architecture Programmer's Manual Volume 1: Application Programming Publication No. 24592 Revision 3. 15 Date November 2009 AMD64 Technology 24592--Rev. 3. 15--November 2009 © 2002 ­ 2009 Advanced Micro Devices, Inc. The contents of this document are provided in connection with Advanced Micro Devices, Inc. [. . . ] In each case, the value of the destination is determined by a field in the immediate-byte operand. SHUFPS is useful, for example, in color imaging when computing alpha saturation of RGB values. In this case, SHUFPS can replicate an alpha value in a register so that parallel comparisons with three RGB values can be performed. operand 1 127 0 127 operand 2 0 imm8 mux mux 127 result 0 513-160. eps Figure 4-34. SHUFPS Shuffle Operation The SHUFPD instruction moves either of the two double-precision floating-point values in the first operand to the low-order quadword of the destination and moves either of the two double-precision floating-point values in the second operand to the high-order quadword of the destination. 4. 6. 5 Arithmetic The floating-point vector-arithmetic instructions perform an arithmetic operation on two floatingpoint operands. Addition · ADDPS--Add Packed Single-Precision Floating-Point · ADDPD-- Add Packed Double-Precision Floating-Point · ADDSS--Add Scalar Single-Precision Floating-Point · ADDSD--Add Scalar Double-Precision Floating-Point 166 128-Bit Media and Scientific Programming 24592--Rev. 3. 15--November 2009 AMD64 Technology The ADDPS instruction adds each of four single-precision floating-point values in the first operand to the corresponding single-precision floating-point values in the second operand and writes the result in the corresponding quadword of the destination. The ADDPD instruction performs an analogous operation for two double-precision floating-point values. Figure 4-35 on page 167 shows a typical arithmetic operation on vectors of floating-point singleprecision elements--in this case an ADDPS instruction. The instruction performs four arithmetic operations in parallel. operand 1 127 0 127 operand 2 0 FP single FP single FP single FP single FP single FP single FP single FP single . . operation . operation . . 127 . 0 FP single FP single FP single FP single result 513-164. eps Figure 4-35. ADDPS Arithmetic Operation The ADDSS instruction adds the single-precision floating-point value in the low-order doubleword of the first operand to the single-precision floating-point value in the low-order doubleword of the second operand and writes the result in the low-order doubleword of the destination. The ADDSD instruction adds the double-precision floating-point value in the low-order quadword of the first operand to the double-precision floating-point value in the low-order quadword of the second operand and writes the result in the low-order quadword of the destination. Horizontal Addition · HADDPS--Horizontal Add Packed Single-Precision Floating-Point · HADDPD--Horizontal Subtract Packed Double-Precision Floating-Point The HADDPS instruction adds the single-precision floating point values in the first and second doublewords of the destination operand and stores the sum in the first doubleword of the destination operand. It adds the single-precision floating point values in the third and fourth doublewords of the destination operand and stores the sum in the second doubleword of the destination operand. It adds the single-precision floating point values in the first and second doublewords of the source operand and stores the sum in the third doubleword of the destination operand. It adds single-precision floating 128-Bit Media and Scientific Programming 167 AMD64 Technology 24592--Rev. 3. 15--November 2009 point values in the third and fourth doublewords of the source operand and stores the sum in the fourth doubleword of the destination operand. The HADDPD instruction adds the two double-precision floating point values in the quadword halves of the destination operand and stores the sum in the first quadword of the destination. It adds the values in the two quadword halves of the source register and stores the sum in the second quadword of the destination register. Subtraction · SUBPS--Subtract Packed Single-Precision Floating-Point · SUBPD--Subtract Packed Double-Precision Floating-Point · SUBSS--Subtract Scalar Single-Precision Floating-Point · SUBSD--Subtract Scalar Double-Precision Floating-Point The SUBPS instruction subtracts each of four single-precision floating-point values in the second operand from the corresponding single-precision floating-point value in the first operand and writes the result in the corresponding quadword of the destination. The SUBPD instruction performs an analogous operation for two double-precision floating-point values. For vectors of n number of elements, the operations are: operand1[i] = operand1[i] - operand2[i] where: i = 0 to n ­ 1 The SUBSS instruction subtracts the single-precision floating-point value in the low-order doubleword of the second operand from the corresponding single-precision floating-point value in the low-order doubleword of the first operand and writes the result in the low-order doubleword of the destination. The SUBSD instruction subtracts the double-precision floating-point value in the low-order quadword of the second operand from the corresponding double-precision floating-point value in the low-order quadword of the first operand and writes the result in the low-order quadword of the destination. Horizontal Subtraction · HSUBPS--Horizontal Subtract Packed Single-Precision Floating-Point · HSUBPD--Horizontal Subtract Packed Double-Precision Floating-Point The HSUBPS instruction subtracts the packed-singled precision operand in the second doubleword of the destination register from that in the first doubleword of the destination register and stores the result in the first doubleword of the destination register. [. . . ] 47 XMM registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 XOR instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 XORPS instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 Y Y bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . [. . . ]