User manual ABIT KR7A-133R V1.00

[. . . ] Copyright and Warranty Notice The information in this document is subject to change without notice and does not represent a commitment on part of the vendor, who assumes no liability or responsibility for any errors that may appear in this manual. No warranty or representation, either expressed or implied, is made with respect to the quality, accuracy or fitness for any particular part of this document. In no event shall the manufacturer be liable for direct, indirect, special, incidental or consequential damages arising from any defect or error in this manual or product. Product names appearing in this manual are for identification purpose only and trademarks and product names or brand names appearing in this document are the property of their respective owners. [. . . ] KR7A-133/KR7A-133R Introducing the BIOS 3-19 PCI2 Master 0 WS Write: Two options are available: Enabled or Disabled. When Enabled, writes to the PCI2 bus are executed with zero wait state (immediately) when PCI2 bus is ready to receive data. If set to Disabled, the system will wait one state before data is written to the PCI2 bus. When you set it to Enabled, it can enable PCI post write buffers to minimize PCI1 master read latency. When you set it to Enabled, it can enable PCI post write buffers to minimize PCI2 master read latency. PCI Delay Transaction: Two options are available: Disabled or Enabled. The chipset has an embedded 32-bit posted write buffer to support delay transactions cycles. Select Enabled to support compliance with PCI specification version 2. 1. Some special peripherals need to use a memory block located between 15M and 16M. System BIOS Cacheable: Two options are available: Disabled or Enabled. When you select Enabled, you get faster system BIOS executing speed via the L2 cache. When you select Enable, you get faster video RAM executing speed via the L2 cache. You must check your VGA adapter manual to find out if any compatibility problems will occur. User's Manual 3-20 Chapter 3 3-5. Integrated Peripherals In this menu, you can change the onboard I/O device, I/O port address and other hardware settings. Figure 3-6A. Integrated Peripherals Menu Default Screen VIA OnChip IDE Device: This item can let you sets several items concerning the VIA OnChip IDE device parameters. Figure 3-6B. VIA OnChip IDE Device Screen KR7A-133/KR7A-133R Introducing the BIOS 3-21 IDE Prefetch Mode: Two options are available: Disabled or Enabled. The onboard IDE drive interfaces supports IDE prefetching for faster drive accesses. If you install a primary and/or secondary add-in IDE interface, set this field to Disabled if the interface does not support prefetching. Onboard IDE-1 Controller: The onboard IDE 1 controller can be set as Enabled or Disabled. " Master Drive PIO Mode: !Auto: The BIOS can auto-detect the transfer mode of the IDE devices in order to set its data transfer rate (Default). You can select the PIO mode from 0 to 4 of the IDE devices in order to set its data transfer rate. " Slave Drive PIO Mode: !Auto: The BIOS can auto-detect the transfer mode of the IDE devices in order to set its data transfer rate (Default). You can select the PIO mode from 0 to 4 of the IDE devices in order to set its data transfer rate. " Master Drive Ultra DMA: Ultra DMA is a DMA data transfer protocol that utilizes ATA commands and the ATA bus to allow DMA commands to transfer data at a maximum burst rate of 100 MB/sec. !Disabled: If you encounter the problem of using Ultra DMA devices, you can try to set this item to Disabled. [. . . ] Your ABIT authorized distributor should be able to provide the fastest solution to your technical problem. We sell our products through distributors who sell to resellers and stores. Your reseller should be very familiar with your system configuration and should be able to solve your problem much more efficiently than we could. After all, your reseller regards you as an important User's Manual E-2 Appendix E customer who may purchase more products and who can urge your friends to buy from him or her as well. [. . . ]