User manual ABIT AV8

[. . . ] AV8 AMD Athlon 64TM (FX) System Board Socket 939 User's Manual 4200-0400-01 Rev. 1. 00 Copyright and Warranty Notice The information in this document is subject to change without notice and does not represent a commitment on part of the vendor, who assumes no liability or responsibility for any errors that may appear in this manual. No warranty or representation, either expressed or implied, is made with respect to the quality, accuracy or fitness for any particular part of this document. In no event shall the manufacturer be liable for direct, indirect, special, incidental or consequential damages arising from any defect or error in this manual or product. [. . . ] When set to "By SPD", the BIOS will read the DRAM module SPD data and automatically set to the values stored in it. The system may be unstable or unable to boot up if your DRAM module does not support the clock you set. When set to [By SPD], the BIOS will read the DRAM module SPD data and automatically set the DRAM clock by the value stored in it. DRAM Command Rate: Two options are available: 2T Command or 1T Command. When the host (northbridge) locates the desired memory address, it then processes the wait state of commands. You can select SDRAM CAS (Column Address Strobe) latency time according your SDRAM specification. RAS# to CAS# Delay: This item specifies the RAS# active to CAS# read write delay time to the same bank. Row Cycle Time: This item specifies the RAS# active to RAS# active time or auto refresh time of the same bank. Row Refresh Cycle Time: This item specifies the auto refresh active to RAS# active time or RAS# auto refresh time. RAS# to RAS# Delay: This item specifies the RAS# active to RAS# active delay time of different bank. Write Recovery Time: This item specifies the time measured from the last write datum is safely registered by the DRAM. Write to Read Delay: This item specifies the time measured from the rising edge following the last non-masked data strobe to the rising edge of the next read command. Read to Write Delay: This item specifies the read to write delay. AV8 BIOS Setup 3-17 Back to Advanced Chipset Features Setup Menu: LDT & PCI Bus Control: Click <Enter> key to enter its submenu: Upstream/Downstream LDT Bus Width: This item allows you to select LDT Bus Width. PCI Master 0 WS Write: Two options are available: Enabled or Disabled. When Enabled, writes to the PCI bus are executed with zero wait state (immediately) when PCI bus is ready to receive data. If it is set to Disabled, the system will wait one state before data is written to the PCI bus. The default is Enabled, When Enable, data transmission from CPU to PCI bus are buffered and compensate for the different speed between CPU and PCI bus. If it is set to Disabled, data transmissions are not buffered and CPU must wait until the data transmission is complete and then start another transmission cycle. The default setting is Driven. Back to Advanced Chipset Features Setup Menu: Memory Hole: When set to [15M­16M], the memory address space at 15M-16M will be reserved for ISA expansion cards that specifically requires this setting. Vlink Data Rate: This item can let you select the Vlink Data Rate between northbridge and southbridge. Integrated Peripherals OnChip IDE Device: Click <Enter> key to enter its submenu: SATA RAID ROM: This item allows you to use the boot ROM of on-chip Serial ATA RAID to boot-up system. IDE Bus Master: This option enables or disables the IDE bus mastering capability under the DOS environment. [. . . ] After all, your reseller regards you as an important customer who may purchase more products and who can urge your friends to buy from him or her as well. They should know best what your system configuration is and your problem. If you feel that you need to contact ABIT directly you can send email to the ABIT technical support department. First, please contact the support team for the branch office closest to you. [. . . ]